FM0+ S6E1C3 Deep Standby Stop Mode

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ErLi_4223826
Level 2
Level 2
First reply posted First question asked First like given

Hi, there

I was trying to trying to put the mcu to a low-power standby mode. Here is the pseudo codes:

while (1)

{

     if(low_power_mode)

     {

          SCB->SCR |= 0x04;     // Enable Deep Sleep Mode

          FM_DS->PMD_CTL = 0x00;     // Standby Stop Mode

          FM_CRG->STB_CTL |= 0x1ACC0006;     // Deep Standby Mode

         

          FM_DS->RCK_CTL &= 0x02;     // stop supplying Clock to RTC macro

          FM_DS->DSRAMR = 0x03;     // SRAM retention enable.

          FM_CRG->CSV_CTL &= 0xFFFC;    // Clear Sub-Clock Supervisor Reset and interrupt.

          __disable_irq();

          __WFI();

     }

}

I use MDK as my development environment and the PDL version is 2.1.

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1 Solution

As we communicated, you have to manually cut off the burried lines on DVK board to measure the power consumption through J5.

View solution in original post

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4 Replies
ErLi_4223826
Level 2
Level 2
First reply posted First question asked First like given

For some reason, the question is posted without me completing it.

Any way, alternatively, I also used the PDL function such as Lpm_GoToStandByMode() to put the system in deep Standby Stop mode, and the current consumption is the same as 0.15 mA or so. I was expecting it to be much lower than this. The mcu is S6E1C3 of type 3. Before entering the while loop, the only module turned on is the external interrupt on NMI pin so that I can wake it up from deep sleep.

I use an external crystal as the secondary clock source on pins X0A and X1A. According to the datasheet, all clocks are turned off at Deep Standby Stop Mode. Assuming there is no other current sink on the PCB, is 0.15 mA looks normal ?

I read the peripheral manual in detail, particularly on Chapter 2-1, 5-4 and 6-1. I don't think, yet I might, miss anything to further lower the power consumption.

Any comment on this deep Standby Stop mode current ?

Thank you.

Eric

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The measured value looks a bit high. You tested on your custom board?

According to the remark shown in device datasheet, all ports need to be fixed / LVD under off, and CALDONE bit is "1".

pastedImage_0.png

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Hey, WangS_81

Thanks for your comments. I followed your suggestions and didn't see any current consumption reduction.

Any more ideas ?

Thank you.

Regards,

Eric

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As we communicated, you have to manually cut off the burried lines on DVK board to measure the power consumption through J5.

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