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PineTree
New Contributor

I want to share with others how to get two synch waveforms with DMA, because it took me some time to figure it out. 

I started with https://www.cypress.com/documentation/application-notes/an52705-psoc-3-and-psoc-5lp-getting-started-... example nr 3, memory to periphery.

Then I wanted to DMA channels feeding 2 DACs and get two synch sine waves at the output.

The bus clock was e.g. at 24MHz (default) and I triggered each burst (you can set each burst or all in the DMA config) with a 1MHz clock at both drq inputs of the DMA blocks.

As explained in the advanced DMA topics Application Note AN84810 (https://www.cypress.com/file/46156/download) you can calculate how many bus clock cycles (=CPU clock cylces) one byte DMA mem-periphery transfer takes (N+7). For two channels accessing the same resources those have to happen after each other.

But both sine signals at the DAC outputs where not in synch.

The problem was that the drq was connected directly to a 1MHz clock. In main.c the both CyDmaChEnable(DMA_1_Chan, 1); CyDmaChEnable(DMA_Chan, 1); were called after each other, which starts one channel slightly before the other.

To fix the problem was to first enable both channels and then using a AND gate and a control register to switch the 1MHz clock to both drq's of the DMAs. Then they start at the same time.

Your waveform generator is limited to how long it takes to load all values to the DACs from memory.

See example Eg3_Mem_DMA_DAC.....

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1 Solution
odissey1
Honored Contributor II

PineTree,

Generally, using two independent WaveDac8 modules doesn't guarantee synchronicity of the output waves. DMA channels are prone to slipping the cycle at high load, which leads to waveforms dissync. For example, such overload will happen for 2 DMA channels outputting ~8kHz sine each of 256 points (48MHz BUS_CLK /256 points/11 clocks_per_DMA /2 channels = 8.5kHz). Once it reaches that frequency, the DMA starts skipping cycles and sync is lost.

    There is another method proposed by the <pavloven>, which guarantees synchronicity of the waves, even if DMA cycle had slipped. You may find updated project here

The project uses intermediate location in RAM to keep wave data, from which it further passed to VDAC target.

/odissey1

DMA8x3_01a.png

DMA8x3_01b.jpg

View solution in original post

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3 Replies
Len_CONSULTRON
Honored Contributor II

PineTree,

Thanks for your project and your results.

I have found the same thing.  In order to sync two (or more) Wave DACs, I needed to synchronize the input external clocks.  By just _Start()ing the two WaveDACs in code, there is a significant time delay causing an unpredictable phase delay between the WaveDACs in time.

I'm in the process of creating a variation of the WaveDAC8 component with an optional "SYNC" input with basically your "AND" gate clock input front end.

Suggestion:  Go to the "Code Examples" forum and post a thread with a link to this thread.  We who have contributed project examples have used that forum as the place to find useful code examples.

Len
"Engineering is an Art. The Art of Compromise."
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odissey1
Honored Contributor II

PineTree,

The forum allows for inserting images into the post message, so it would be beneficial to add some screenshots of the project pages as well as scope screenshots.

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odissey1
Honored Contributor II

PineTree,

Generally, using two independent WaveDac8 modules doesn't guarantee synchronicity of the output waves. DMA channels are prone to slipping the cycle at high load, which leads to waveforms dissync. For example, such overload will happen for 2 DMA channels outputting ~8kHz sine each of 256 points (48MHz BUS_CLK /256 points/11 clocks_per_DMA /2 channels = 8.5kHz). Once it reaches that frequency, the DMA starts skipping cycles and sync is lost.

    There is another method proposed by the <pavloven>, which guarantees synchronicity of the waves, even if DMA cycle had slipped. You may find updated project here

The project uses intermediate location in RAM to keep wave data, from which it further passed to VDAC target.

/odissey1

DMA8x3_01a.png

DMA8x3_01b.jpg

View solution in original post

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