Code Examples Forum Discussions

Hi all,

In order to study how to turn on and control many LEDs, I created a board with a matrix. I decided to make a roulette wheel using 36 LEDs. This time, it will be a program to test this LED display board.

The environment used is as follows:

・PSoC Creator 4.3

・CY8CKIT-044

36 LEDs are mounted on the Arduino board, and 12 GPIOs are used to configure a 6x6 matrix. The circuit looks like this:

The actual Arduino board was made as shown in the picture below. There were quite a lot of wiring and it got messed up.

The circuit creates a counter to count 6 by combining the components of Coutner and Compare in column side. It is used to select the De-Multiplexer to select the output. The row side of the LED matrix is ​​switched half alternately after 6 counts. As a result, the lighting of the three LEDs moves to shift. This will ensure that the LED board wiring is correct. The circuit and pin layout are as follows.

Since the purpose is to check the lighting of the LED, the PWM output is set to a slow frequency with a 5KHz clock as the input.

The program just starts PWM_1.

#include "project.h"
int main(void)
{
    CyGlobalIntEnable; /* Enable global interrupts. */
    /* Place your initialization/startup code here (e.g. MyInst_Start()) */
    PWM_1_Start();
    
    for(;;)
    {
        /* Place your application code here. */
    }
}

If the connection is successful, the lights will be as shown below.

Thanks,

Kenshow

Hi,

Provided below is basic o-scope demo, operating in hardware triggered mode. It can be used for acquiring fast transients using PSoC5 SAR_ADC.

Two modes of operation are shown:

1. ADC is operating in free-running mode, while DMA is set to "Ready" mode, waiting for a hardware trigger. Once external trigger is detected, DMA transfers pre-defined number of points (N=200) into RAM buffer, and fires interrupt once completed.

2.. ADC is operating in clocked mode. ADC clock is first set to "Ready" mode, waiting for a hardware trigger. Once external trigger is detected, ADC starts acquiring data, which is transferred to RAM buffer by DMA. Once pre-defined number of points (N=200) has been transferred, DMA fires interrupt.

Acquired data is then being transferred by UART and plotted by external charting tool SerialPlot (by Yavuz Ozderya).

In this example, the device under test (DUT) is simply a KIT-059 onboard 2.4nF capacitor (C4), which is being charged/discharged through the digital output pin configured in Resistive Pull Up/Down mode.

As shown, ADC sampling rate is 1MHz, resolution 8-bit, N acquired points = 200. The ADC can be overclocked to about 1.7 MHz using clocked mode.

This project uses several custom Community components and libraries:

     SerialPlot: SerialPlot: interface to real-time data charts

     PSoC Annotation Library: PSoC Annotation Library v1.0

     Yavuz Ozderya, Serial PLOT v0.10.0,  https://hasanyavuz.ozderya.net/?p=244

/odissey1

Figure 1. ADC in free-running mode. DMA is h/w triggered.

Figure 2. ADC in clocked mode. DMA is clocked by ADC's end-of-sampling (eos).

Figure 3. Pulse train generator for testing. Pulse delay - 20us, pulse length - 20us, repetition - 100Hz. The DUT is KIT-059 onboard capacitor C4 (2.4nF), driven by the digital Pin_150, configured for Resistive Pull Up/Down.

Figure 4. SerialPlot custom component for plotting acquired data. configured for Simple Binary, 1-channel, uint8 data.

Figure 5. Project annotation using PSoC Annotation Library 1.0.

Figure 6. Oscilloscope traces: Yellow - DUT, Cyan - PWM pulse, Fuchsia - ADC trigger pulse.

Figure 7. SerialPlot output and DataFormat window.

Attached below is a demo project showing RMS (Root Mean Square) measurement using weighting function technique. In such approach ADC is continuously sampling the signal, and RMS is calculated over finite interval of ~10 AC periods using a weighted window. This simple approach works if signal frequency variations are within pre-defined range, and high output rate is not needed. It can work for non-demanding application such as 50-60 Hz AC monitoring.

The idea is illustrated on Chart 1.

Chart 1. Calculated AC signal, signal squared, weighting window and their product.

AC signal simulated by the Cosine (10 periods), and weighting function by the Gaussian, calculated over 1001 points (1000 intervals).

Cosine = cos( 2 * PI * Freq *  X ); Gauss = exp( -(X^2 / (2 * sigma^2) ), and where Freq = 10 and sigma = 250. The pseudocode is provided here:

Re: bounces happened at comparator output

Despite the weighting function here is being clipped, the calculated RMS = 0.707106 matches theoretical value sqrt(1/2).

The project uses double-buffering technique. The incoming AC signal is continuously sampled using PSoC5 DeltaSigma ADC (16-bit) and transferred to the ring Buffer in RAM by DMA. Once half of Buffer is filled, the interrupt is fired requesting data processing, while DMA continues to populate the Buffer in the background. RMS update frequency is defined by the size of the Buffer and ADC sampling rate. ADC sampling rate determines amount of harmonics captured, thus the accuracy of the measurements. Note that this approach does not require synchronizing the ADC sampling clock and AC signal, which makes it very simple and portable to PSoC4 and PSoC6.

Data below shown for ADC sampling rate of 2 kHz and Buffer size of 2x401 samples. Resulting RMS update rate was approx. 5 Hz. Project was also tested using other parameters: ADC-1, 2, 4, 8 kHz, 1/2 Buffer size - 201, 401 and 801 samples.

Project includes optional arbitrary signal generator, which can be safely removed if external signal generator is available. It requires following custom components:

*   DDS32 v0.0                  : Arbitrary frequency DDS generator. https://community.cypress.com/message/158566#158566

*   WaveGen8 v0.0 (beta) : Arbitrary shape wave generator (included into this project)

*   QuadDec_SW v0.1      : Quad decoder w/button switch. https://community.cypress.com/thread/30654

Other optional custom component used in the project:

*   PSoC Annotation Library v1.0: https://community.cypress.com/message/204321

*   StopWatch v0.0 (beta)  : Timer for code profiling (included into this project)

Also attached a stripped down version of the project (without signal generator and other external components). This may help if external signal generator is available.        

/odissey1

Figure 1. Project schematic.

Figure 2. Project timing diagram

Figure 3. Optional arbitrary signal generator.

Figure 4. KIT-059 Circuit diagram using PSoC Annotation Library v1.0.

Figure 5. Yellow trace - AC signal input; Cyan - signal reference; Fuchsia - RMS voltage output.

Figure 6. UART terminal output.

Hi,

In the previous post it was shown how to use DMA with DelSig-ADC and Filter (PSoC5).

DelSig_ADC - Filter - VDAC8 streaming demo using DMA

Provided below is similar project, but utilizing ADC_SAR instead of the DelSig-ADC.

Provided below are 3 projects:

1. SAR-Filter-VDAC_01c_stripped.cydsn

Standard ADC_SAR-Filter-VDAC demo, exemplifying the ADC_SAR issues:

   * ADC_SAR is not performing correctly in the differential mode. The ADC_SAR output is always unsigned (0-4095) no matter if input is configured for differential or single mode (the DelSig-ADC correctly outputs -2048 to 2047 in the differential mode).

   * The Filter input expects signed 16-bit data, but ADC_SAR produces only 12-bit unsigned data. This 4-bit offset can't be corrected by DMA alone.

As a result, a simple DMA transfer ADC-Filter-VDAC results in very weak output, 1/16 of the VDAC8 full output scale.

2. SAR-Filter-VDAC_signed_FIFO_02a.cydsn

Enhanced demo, where the ADC_SAR output is first converted from unsigned to 2's compliment, and then scaled up by 4 bits to make a 16-bit signed data, which is captured by the FIFO and transferred to the Filter by DMA1. The Filter output is also signed, so it converted back to unsigned (uint8) using external logic, and transferred to VDAC using DMA2 with chained TDs.

3. SAR-Filter-VDAC_unsigned_FIFO_02a.cydsn

Simplified demo, where the ADC_SAR output is NOT converted from unsigned to 2's compliment. It is just scaled up by 3 bits to make a 15-bit unsigned data, which is captured by the FIFO and transferred to the Filter by DMA1. The filter output is UN-signed, so it can be sent directly to VDAC8 by DMA2. The Filter gain is doubled to compensate for amplitude loss.

/odissey1

Project uses several custom Community components, which are included in the project. A full version of the project has sine generator included. A stripped version of the project has sine generator removed. It can be used if external function generator is available.

     * ADC_SAR_ex: Re: Best Approach: Implement DMA on 16bit Timer or 2 Status Registers?   (included in the project)

     * FIFOin: Re: Best Approach: Implement DMA on 16bit Timer or 2 Status Registers? (included in the project)

     * BusConnect: BusConnect: virtual interface for digital hardware bus (included in the project)

     * WaveGen8 (RAM-DMA-VDAC8 wave generator, included in the project)

     * QuadDecoder_SW: Re: Quad Decoder with Button Switch component for rotary shaft encoders

     * DDS32: Re: DDS24: 24-bit DDS arbitrary frequency generator component

     * optional PSoC Annotation Library: PSoC Annotation Library v1.0

Presented Below are screenshots from the "enhanced" project SAR-Filter-VDAC_signed_FIFO_02a.cydsn

Figure 1. ADC_SAR-Filter page schematic. ADC result is converted from 12-bit unsigned to to 16-bit 2's complement. The Filter gain = 1.

Figure 2. Filter-VDAC page schematic. Filter result converted from 2's complement to 8-bit unsigned using DMA2 two chained TDs.

Figure 3. Optional signal (sine) generator for project testing. It is not included in the stripped version of the project, which requires external signal generator for testing.

Figure 4. Project annotation (made using optional PSoC Annotation Library v1.0 ). Note the ADC input bias is taken directly from the bias capacitor C12. This schematic is shared among all projects.

Figure 5. Cyan - 1 kHz ADC signal input, Yellow trace - VDAC output, Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=1.

Figure 6. Cyan - 5 kHz ADC signal input, Yellow trace - VDAC output, Fuchsia - signal reference.. Filter configured for LPF, Fc=5kHz, Gain=1.

Figure 7. Cyan - 6 kHz ADC signal input, Yellow trace - VDAC output, Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=1.

Hi,

Provided below is a custom component, BusConnect v1.0, which provides easy interfacing of two digital buses of mismatching sizes.

The component facilitates (I) connection of the narrow output to wide input, and (II) connection of wide output to a narrow input. The component is virtual, it doesn’t consume system resources. Using BusConnect component saves space and simplifies schematic. Component is compatible with PSoC4 and PSoC5 (PSoC6 - untested).

Attached archive contains the component library, a Datasheet and installation instructions. Upon installation it will show up in the folder:

/Community/Digital/Utilities/

The component provided as-is, no liabilities. It is free to use, modify and distribute.

Regards,

/odissey1

Figure 1.  The BusConnect appearance for bits injection and its equivalent representation.

Figure 2. Example of hardware Voltage Controlled Oscillator (VCO) with adjustable gain.

Figure 3. Example of hardware chirp generator for ultrasound range finder.

Hi all,

Through this programing of the dice, I was able to learn various PSoC designs. I've considered 7LEDs dice with ModusToolbox, but I gave up because ModusToolbox doesn't have a tool like the circuit input of PSoC Creator. In addition, Creator generats C functions using the created component name, so it was easy to program. Unfortunately, in MTB, it is necessary to make detailed settings with the cy_ function, and there are few CEs that use the function when using Device Configurator, which causes confusion in how to use the cy_ function.

Add a BEEP sound to the one created in the previous DMA transfer. I also created this in PSoC Creator, but arranged it for Modus Toolbox 2.2. I hope you can see it as one of the CEs that control PWM from PWM.

The environment used is as follows:

・ModusToolbox 2.2

・CY8CKIT-062-BLE

See the previous post for LED board circuitry and the concept of DMA.

Let's make the dice of seven eyes on PSoC 6 with DMA for ModusToolBox2.2

When using Creator, I designed the beep sound with the following circuit. However, for ModusToolbox, the pwm output in PWM cannot be used for the next PWM control input. Therefore, we have to use Device Configurator. Device Configurator in Modus Toolbox can faithfully reproduce the PSoC 6 MCU Trigger Multiplexer and help you find this route.

Since the Beep output is decided to Pin10 [0], you can see that the output of TCPWN [0] 32bit counter 6 can be used by setting from pin with Device Configurator. 

In the case of ModusToolbox, pwm output of the PWM cannot be used for the next PWM control input, so use ovrflw and Compare of PWM_1 to control the Start / Stop of PWM_2. The settings of the Device Configurator of PWM_2 to be added are as follows.

The clock settings for PWM_2 are as follows.

The Pin settings are as follows. Drive Mode is set to LEDx and Buzzer pin: "Strong Drive, Input buffer off", SW2: "Resistive Pull-Up, Input Buffer on".

The program only adds the PWM_2 settings.

#include"cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"
 
uint32 Buffer[12]={0x37,0x01,0x1D,0x01,0x15,0x01,0x1C,0x00,0x14,0x00,0x08,0x00};
uint32_t sw=0;  //sw is off (Stop rolling dicce)
int main(void)
{
    cy_rslt_t result;
 
    /* Initialize the device and board peripherals */
    result = cybsp_init() ;
    if (result != CY_RSLT_SUCCESS)
    {
        CY_ASSERT(0);
    }
 
    __enable_irq();
 
    //DMA_1_Start ((void const *)Buffer, (void const *)0x40320280);
    if (CY_DMA_SUCCESS != Cy_DMA_Descriptor_Init(&DMA_1_Descriptor_0, &DMA_1_Descriptor_0_config))
    {
        while(1); // Handle Error
    }
    if(CY_DMA_SUCCESS != Cy_DMA_Channel_Init(DMA_1_HW, DMA_1_CHANNEL, &DMA_1_channelConfig)){
        while(1); // Handle Error
    }
 Cy_DMA_Descriptor_SetSrcAddress(&DMA_1_Descriptor_0, (void const *)Buffer);
 Cy_DMA_Descriptor_SetDstAddress(&DMA_1_Descriptor_0, (void const *)0x40320280);
 Cy_DMA_Descriptor_SetNextDescriptor(&DMA_1_Descriptor_0, &DMA_1_Descriptor_0);
    Cy_DMA_Channel_Enable(DMA_1_HW, DMA_1_CHANNEL);
    Cy_DMA_Enable(DMA_1_HW);
 
Cy_TCPWM_PWM_Init(PWM_2_HW, PWM_2_NUM, &PWM_2_config);
    Cy_TCPWM_PWM_Enable(PWM_2_HW, PWM_2_NUM);
 
    for (;;)
    {
        if(sw==0){
            if(Cy_GPIO_Read(SW2_PORT,SW2_NUM)==0){
                Cy_TCPWM_PWM_Init(PWM_1_HW, PWM_1_NUM, &PWM_1_config);
                Cy_TCPWM_PWM_Enable(PWM_1_HW, PWM_1_NUM);
                 Cy_TCPWM_TriggerStart(PWM_1_HW, PWM_1_MASK);
                sw=1;
            }
        }
        if(sw==1){
            if(Cy_GPIO_Read(SW2_PORT,SW2_NUM)==1){
                /* Roll dice slowly */
 Cy_TCPWM_TriggerCaptureOrSwap(PWM_1_HW, PWM_1_MASK);
                CyDelay(1500);  // keep rolling slowly for 1.5sec
                Cy_TCPWM_PWM_Disable (PWM_1_HW, PWM_1_NUM);
                sw=0;           // sw is off
            }
        }
    }
}
 
/* [] END OF FILE */

Usage: Press SW2 to rotate the dice and release it to slow down and stop.

Thanks,

Kenshow

Hi all,

Through this programing of the dice, I was able to learn various PSoC designs. I've considered 7LEDs dice with ModusToolbox, but I gave up because ModusToolbox doesn't have a tool like the circuit input of PSoC Creator. In addition, Creator generats C functions using the created component name, so it was easy to program. Unfortunately, in MTB, it is necessary to make detailed settings with the cy_ function, and there are few CEs that use the function when using Device Configurator, which causes confusion in how to use the cy_ function.

Last time, I was able to express a 7LED dice with DMA of PSoC6, so I can create it on MTB without a circuit input tool. I hope you can see it as a CE of DMA that kicks from PWM.

The environment used is as follows:

・ModusToolbox 2.2

・CY8CKIT-062-BLE

The DMA trigger inputs PWM overflow. The circuit image is as follows. 

The DMA transfer is the following image.

Set this in Device Configurator. The settings for DMA_1 are shown below.

The PWM_1 settings are shown below. The period can be changed with swap.

The clock settings for PWM_1 are as follows.

The Pin settings are as follows. Drive Mode is set to LEDx pin: "Strong Drive, Input buffer off", SW2: "Resistive Pull-Up, Input Buffer on".

The program on CM4 is as follows:

#include"cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"
 
uint32 Buffer[12]={0x37,0x01,0x1D,0x01,0x15,0x01,0x1C,0x00,0x14,0x00,0x08,0x00};
uint32_t sw=0;  //sw is off (Stop rolling dicce)
int main(void)
{
    cy_rslt_t result;
 
    /* Initialize the device and board peripherals */
    result = cybsp_init() ;
    if (result != CY_RSLT_SUCCESS)
    {
        CY_ASSERT(0);
    }
 
    __enable_irq();
 
    //DMA_1_Start ((void const *)Buffer, (void const *)0x40320280);
    if (CY_DMA_SUCCESS != Cy_DMA_Descriptor_Init(&DMA_1_Descriptor_0, &DMA_1_Descriptor_0_config))
    {
        while(1); // Handle Error
    }
    if(CY_DMA_SUCCESS != Cy_DMA_Channel_Init(DMA_1_HW, DMA_1_CHANNEL, &DMA_1_channelConfig)){
        while(1); // Handle Error
    }
 Cy_DMA_Descriptor_SetSrcAddress(&DMA_1_Descriptor_0, (void const *)Buffer);
 Cy_DMA_Descriptor_SetDstAddress(&DMA_1_Descriptor_0, (void const *)0x40320280);
 Cy_DMA_Descriptor_SetNextDescriptor(&DMA_1_Descriptor_0, &DMA_1_Descriptor_0);
    Cy_DMA_Channel_Enable(DMA_1_HW, DMA_1_CHANNEL);
    Cy_DMA_Enable(DMA_1_HW);
 
        //Cy_TCPWM_PWM_Init(PWM_2_HW, PWM_2_NUM, &PWM_2_config);
    //Cy_TCPWM_PWM_Enable(PWM_2_HW, PWM_2_NUM);
 
    for (;;)
    {
        if(sw==0){
            if(Cy_GPIO_Read(SW2_PORT,SW2_NUM)==0){
                Cy_TCPWM_PWM_Init(PWM_1_HW, PWM_1_NUM, &PWM_1_config);
                Cy_TCPWM_PWM_Enable(PWM_1_HW, PWM_1_NUM);
                 Cy_TCPWM_TriggerStart(PWM_1_HW, PWM_1_MASK);
                sw=1;
            }
        }
        if(sw==1){
            if(Cy_GPIO_Read(SW2_PORT,SW2_NUM)==1){
                /* Roll dice slowly */
 Cy_TCPWM_TriggerCaptureOrSwap(PWM_1_HW, PWM_1_MASK);
                CyDelay(1500);  // keep rolling slowly for 1.5sec
                Cy_TCPWM_PWM_Disable (PWM_1_HW, PWM_1_NUM);
                sw=0;           // sw is off
            }
        }
    }
}
/* [] END OF FILE */

Usage: Press SW2 to rotate the dice and release it to slow down and stop.

Thanks,

Kenshow

Hello,

KBA225808 can be tried up to V6.0 of CSD.

CSD V7.0 requires a program modification.

The following of main.c has been changed.

Please see the following thread.

Measure Cmod and Cp of PSoC 4S CapSense for CSD V7.0

Up to CSD V6.0   [The unit of u8_cpValue[] are pF(picofarad).]

From CSD V7.0  [The unit of u8_cpValue[] are fF(femtofarad).]

Be sure to set the following definition in main.c to 0.

(Set to 1 to enable CapSense Tuner.)

Build this project and program it into CY8C4045AZI-S413 of CY8CKIT-145-40XX.

Here, if a program for I2C communication with CY8C4045AZI-S413 is written in CYBLE-022001-00, it will not work properly.

Use the PSoC Programmer to erase the CYBLE-022001-00 program.

Launch the Bridge Control Panel and follow the steps below to open V70_2ch Cp.iic and V70_2ch Cp.ini.

1. [File] -> [Open File...] -> [V70_4ch Cp.iic] open

2. [Chart] -> [Variable Settings] -> [Loading...] in Submenu -> [V70_4ch Cp.ini] open -> [OK] in Submenu

3. Click the following line in the [Editor] tab.

r 08 x x x x x @0WID0 @1WID0 @2WID0 @3WID0 @0WID1 @1WID1 @2WID1 @3WID1 p

4. Select the [Chart] tab next to the [Editor] tab and click [Repeat].

    Then, touch SLD0(0.0) and SLD4(0.6).

Click the next line  in the [Editor] tab if you want to see the Cmod value.

r 08 x @0CMOD @1CMOD @2CMOD @3CMOD x x x x x x x x p

And change the valiable settings of [Chart].

Best regards,

Yocchi