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This is a demo project showing generation of the quadrature signal from the externally provided clock (of arbitrary frequency). The second demo project shows generation of phase-shifted output signal for arbitrary phase. Such necessities often arise in lock-in signal demodulation, when the reference clock comes from the external source (signal generator) and phase-shifted ( or quadrature) signal has to be synthesized internally from that clock.
The project targets high-frequency range (~100kHz), where achieving good-quality phase rotation without phase jitter becomes problematic. This jitter comes from 1 BUS_CLK uncertainty when sampling external signal.
The project uses digital Counter to measure period of the input clock and to generate a phase-shifted (quadrature) copy of it. To achieve low phase noise (jitter/period is ~0.1% or better), PSoC must operate at highest frequency possible (80 MHz). Unfortunately, the standard Counter component (v3.0) is limited to about 63 MHz, and can count at highest sampling rate of BUS_CLK / 4, which yields phase noise of about 0.6%: jitter / period = 4 x 100kHz / 65MHz = 0.6%.
To achieve better accuracy, the standard Counter (v3.0) component has been modified to operate at full speed of 80MHz. Updated custom component (Counter_ex) can operate in 8/16/24 and 32-bit modes, counting at full bus speed (80 MHz) with low phase noise: 100 kHz / 80 MHz = 0.125%. The phase noise drops further at lower input frequencies.
Attached are two demo projects and Counter_ex component library showing:
(a) quadrature signal generation while sweeping frequency of the input signal;
(b) sweeping the phase of the output while keeping input signal frequency fixed.
Optional DDS32 component library can be found here: