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The Filter output is signed value (Sine), which, when reaches full amplitude, produces weird output from the VDAC, which treats incoming data as unsigned. To achieve the full scale output, here the data are converted to unsigned using extra logic (Control_Reg, Status_Reg and XOR element to correct highest bit). The DMA channel has been modified to include two Transfer Descriptors. First TD is transferring int8-type data from the Filter to the Control_Reg, and second TD immediately retrieves corrected data from the Status_Reg (uint8) and passes it to the VDAC8.
Project includes several custom Community components, which are used to make internal sine generator with tunable parameters. Those components can be omitted if external function generator is available:
WaveGen8 (RAM-DMA-VDAC8 wave generator, included in the project)
Figure 1. DelSig_ADC to Filter data streaming using DMA
Figure 2. Filter to VDAC data streaming using DMA with two TDs. A signed output value (int8) is converted to the unsigned (uint8) using PLD logic in a single DMA pass.
Figure 3. Function Generator using DDS32, and WaveGen8 custom components
Figure 4. Project annotation diagram using PSoC Annotation Library.
Figure 5. Original demo project by Cypress showing Filter performance at 1 kHz and full swing. Blue trace - ADC input signal, Yellow trace: VDAC_1 output, Fuchsia - WaveGen reference.
Figure 6. Corrected Filter performance at 1 kHz. Blue trace - ADC input signal, Yellow trace: VDAC_1 output, Fuchsia - WaveGen reference. The steps are due to 48kHz ADC sampling rate. Filter LPF cut-off is set to 6kHz.
Figure 7. Filter performance at 6 kHz. Blue trace - ADC input signal, Yellow trace: VDAC_1 output, Fuchsia - WaveGen reference.
Figure 8. Filter performance at 7 kHz. Blue trace - ADC input signal, Yellow trace: VDAC_1 output, Fuchsia - WaveGen reference.
Added Figure 5 - Original project performance at full amplitude swing, showing issue when data is transferred from Filter to VDAC8 directly. Updated project archive now also includes an old DMA_1 configuration to show the issue.
Added a screenshot demonstrating issue with original project, when data was transferred by DMA from Filter to VDAC8 directly. Updated project archive includes old DMA_1 configuration to demo this issue.