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Here I submitting my version of the 24-bit DDS arbitrary frequency generator component. It is useful for applications requiring precision frequency generation. Provided below are: component library, datasheet, application note and several demo projects exemplifying use of the component.
Many thanks to authors of various previous incarnations of DDSs: <PSoC73>, <pavloven>, <vdvorak>, <kabron>, <JLS1>.
This component was developed as part of Warp Verilog study and does not pursue any particular purpose.
Attached below two PSoC4 projects showing a sweep generators based upon DDS24 and DDS32 components. Both projects use software timing (DDS frequency update on interrupt), but have different performance. For example, DDS24 project is limited to approx. 34 MHz of DDS clock, while DDS32 has no limitation. On the other side, DDS24 allows for hardware timing of the output frequency and even secondary (phase-shifted channel), but DDS32 has no such options. Both project use latest DDS components from above.
Figure 1. DDS24-based PSoC4 sweep generator using software timing
Figure 2. DDS32-based PSoC4 sweep generator using software timing
Attached below PSoC4 example of the DDS24 sweep generator using deterministic hardware timing. In this example the DDS24 is configured for hardware load and loads data from the internal register on the rising edge of the load clock. The rfd (ready-for-data) interrupt signals to processor that the next frequency data can be loaded into register.
Figure 1. PSoC4 sweep generator demo with hardware load.