DDS24: 24-bit DDS arbitrary frequency generator component

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Hi,

   

Here I submitting my version of the 24-bit DDS arbitrary frequency generator component. It is useful for applications requiring precision frequency generation. Provided below are: component library, datasheet, application note and several demo projects exemplifying use of the component.

   

   

Many thanks to authors of various previous incarnations of DDSs: <PSoC73>, <pavloven>, <vdvorak>, <kabron>, <JLS1>.

   

This component was developed as part of Warp Verilog study and does not pursue any particular purpose.

   

odissey1

      

video link: DDS tunable frequency / phase generator using Cypress PSoC5 - YouTube

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DDS24_WaveDAC_1a.png

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Doorknob
Level 4
Level 4
First solution authored 50 replies posted 25 replies posted

odissey ... can your DDs24 component work on PSoC4 device?

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Yes, in basic configuration DDS24 can fit P4200 and up. Depending on project needs, it is often possible to substitute it with DDS32, which occupies UDB Datapath space (not PLD).

Check these examples:

DDS32:

Adjustable Active Low Pass Filter for PSoC

How can I handle a PSoC 5 community library DDS24 on PSoC 4 BLE device ?    

DDS32_P4_basic.png

 

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Doorknob,

Attached below two PSoC4 projects showing a sweep generators based upon DDS24 and DDS32 components. Both projects use software timing (DDS frequency update on interrupt), but have different performance. For example, DDS24 project is limited to approx. 34 MHz of DDS clock, while DDS32 has no limitation. On the other side, DDS24 allows for hardware timing of the output frequency and even secondary (phase-shifted channel), but DDS32 has no such options. Both project use latest DDS components from above.

/odissey1

Figure 1. DDS24-based PSoC4 sweep generator using software timing 

DDS24_sweep_sw_P4_01a_A.png

Figure 2. DDS32-based PSoC4 sweep generator using software timing DDS32_sweep_sw_P4_01a_A.png

 

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Attached below PSoC4 example of the DDS24 sweep generator using deterministic hardware timing. In this example the DDS24 is configured for hardware load and loads data from the internal register on the rising edge of the load clock. The rfd (ready-for-data) interrupt  signals to processor that the next frequency data can be loaded into register.

/odissey1

Figure 1. PSoC4 sweep generator demo with hardware load.

DDS24_sweep_hw_P4_01a_A.png 

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Qinova
Level 1
Level 1
First reply posted Welcome!

Hello Odissey1,

I'm using the DDS24 component on PSOC5LP for generating a 40kHz square wave using a 1MHz clock (XTAL24MHz divided by 24). I need both outputs with phased signals to drive a full bridge with a variable DC (obtained by varying phase difference). I can see that the DC is not stable at 50% but varies randomically of 1 clk cycle (and not sincronus in the two outputs).  I see this problems in all the DEMOS but it became evident on slow clocks.

You know this issue? How can we fix the problem?

take a look to the attached videos:

https://youtu.be/LCQRKvhG-G4

https://youtu.be/0W5riqcmi5w

 

Thanks!

 

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Qinova,

The 1 clock jitter of the period is intrinsic to all DDS and is due to the fraction (remainder) of the accumulated TuneWords, which overflows the Accumulator. On each sampling clock the Accumulator is being incremented by TuneWord

Acc = Acc + TuneWord,

where:

TuneWord = Freq/Clock)*(2^24),

and sooner or later it overflows (2^24). It is apparent that if TuneWord doesn't divide 2^24 evenly, the remainder will accumulate, causing this jitter. This jitter gets worst the closer the set frequency to the Nyquist frequency (Clock/2), e.g. 0.5MHz in your case.

General solution is to increase the sampling clock as far as possible, for example 48MHz (instead of 1MHz) The jitter shall remain same 1 clock, but it will be much smaller, compared to the period. Another solution is to select the output frequency precisely so that 

(2^24)/TuneWord = Clock/Freq = integer

For example, 1MHz/40kHz = 25. But the tunability of the DDS output becomes limited, as next "magic" output frequency will be 1MHz/26 = 38.461538461kHz. So the range of tunability becomes same as can be offered by traditional PWM.

My suggestions: if fine resolution of the output frequency is important, increase the Clock frequency to the max allowed by design, e.g BUS_CLK =48MHz. (The clock limit can be found in the Timing file, or by clicking on the warning message). Note that the spacing between the "magic" Frequencies (no jitter) becomes much closer (~34Hz).

If tunability is not important, use traditional PWM. The output will be guaranteed stable.

/odissey1

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