Showing results for 
Search instead for 
Did you mean: 

Code Examples

Honored Contributor II

Recently there was an inquiry about pulse chirp (frequency sweep) generation for ultrasound range detection. It required a burst of the frequency sweep between 38kHz to 42kHz in 5ms for transducer excitation, followed by the 5ms of quiet period for detection of the reflected signal.

The demo project below provides all-hardware solution to this using 24-bit DDS generator (DDS24). The DDS24 is controlled using digital bus, which code is linearly swept in time in 64 steps, provided by the Count7. Project uses unique ability of the DDS to switch output frequency instantly upon tune word change (unlike a PWM, which has to wait until completion of the current period). Project is compiled using CY8CKIT-059 (PSoC5LP). It can be adapted to run on PSoC4/4M series chips.

Project archive is attached below.


Project uses following custom components:

DDS24 v0.1: Re: DDS24: 24-bit DDS arbitrary frequency generator component

The Dummy: The Dummy: empty component for digital bus routing

PSoC Annotation library v1.0: PSoC Annotation Library v1.0

BusConnect_v1_0 (included into the project)

Figure 1. Project schematic.


Figure 2. Connection diagram using PSoC Annotation Library


Figure 3. Scope screenshot: chirp burst (5ms) followed by quiet period (5ms).


Figure 4. Chirp measured starting frequency 38.2kHz


Figure 5. Chirp measured ending frequency 43.1kHz


1 Reply
Honored Contributor II

Attached below is another all-hardware chirp generator demo for ultrasound range finder. Unlike previous project, it utilizes UDB-based DDS32 component, allowing for control of its output frequency by using DMA. It produces 38-to-42 kHz linear 64-steps frequency sweep in 5 ms, followed by the 5 ms of the idle time for echo detection.

Project uses unique ability of the DDS32 to switch the output frequency instantaneously upon the tune word change. The DDS32 frequency output is updated by DMA, transferring the tune word values from the circular RAM buffer directly into DDS register. The Buffer is populated with ramp values on startup, resulting in linearly swept DDS output frequency. The DMA is configured with two chained TDs, providing both for the ramp and for the idle time counter.

Unlike the DDS24 demo, here all parameters (start/stop frequency, ramp/idle time) can be adjusted independently, which gives extra flexibility. Few optional logic elements were added for clock sync, and outputs co-alignment.

Project is compiled using CY8CKIT-059 (PSoC5LP). It consumes only two UDB blocks and can be adapted to run on PSoC4 and PSoC6 series chips.

Project archive is attached below. All necessary components are included into the project.


Figure 1. Project schematic.


Figure 2. Connection diagram using PSoC Annotation Library


Figure 3. Chirp burst test: 1-:-10 kHz ramp in 5ms followed by 5ms of idle period.


Figure 3. Chirp burst 38-42kHz (5ms) followed by idle period (5ms).


Figure 4. Chirp starting frequency approx. 38.2 kHz


Figure 5. Chirp ending frequency approx 42.4 kHz