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类别 | 扇出比 | 工作温度范围 | 封装 | 工作电压 | 输入电平 | 输出电平 | 频率范围 | Phase jitter | skew(最大值) | delay(最大值) |
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单端转单端 | 1:2 |
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1:4 |
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1:6 |
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1:8 |
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(1:5)*2 |
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差分转差分 | 1:2 |
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1:5 |
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1:10 |
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单端转差分 | 1:4 |
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类别 | 扇出比 | 工作温度范围 | 封装 | 工作电压 | 输入电平 | 输出电平 | 频率范围 | Phase jitter | skew(最大值) | delay(最大值) | 月均出货量 |
单端转单端 | 1:2 |
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1:4 |
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1:6 |
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1:8 |
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(1:5)*2 |
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差分转差分 | 1:2 |
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1:5 |
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1:10 |
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单端转差分 | 1:4 |
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XIN/XOUT supports crystal input. Can I feed a TXCO to XIN pin directly?
What is the number of programming that guarantee DECT specification?
(Please see an attached file for DECT of page19 on the datasheet.)
Is it one cycle only or 100k cycles?
Best regards,
Show LessLet us know the programming tools of CY27430.
I think MiniProg3 and Clock programmer for evaluation board. Is it right ?
Do you have 3rd party programming tool for mass production?
Best Regards,
Show LessQ1. If we program configuration to NVM by programming tool, Can CY27430 work without I2C connect?
Q2. If yes for Q1, How do we handle the unused pins of I2C? (Let us know your recommend connection of I2C pins.)
Q3. Do tLOCK spec include I2C operation?
(Please see an attached file for tLOCK of 12page on the datasheet.)
Best Regards,
Show LessDo you have evaluation kit for CY27430?
(i can't found on your web side.)
Best Regards,
Are HOTLink II devices upward compatible with HOTLink devices?
Is it possible to use a HOTLink II device to the HOTLink protocol?
For example, can CYP15G0101DXB be used to replace CY7B923 / 933?
It is using CY7B922 / 933 in current product. I want to realize HOT Link with the next model. I would like to know if HOT Link II devices can be used with the following models.
As far as I read AN1160, I think it can be used.
Thanks,
Tetsuo
Show LessHello,
I have questions below parameters in CY2308 datasheet.
1) t6 Delay, REF rising edge to FBK rising edge : max +/-250ps
Please tell me the meaning of this regulation.
I understand that this rule is not the input condition of the clock buffer, but the maximum value of the phase shift between the REF input and the FBK input when the PLL of the clock buffer is synchronized. Is my understanding correct?
(The clock buffer keeps the deviation between the REF input and the FBK input within this value.)
2) CL, Load capacitance, below 100 MHz : max 30pF
Regarding the capacitance to be added to the CLK A1 output returned to the FBK pin, what will happen if a capacitance exceeding the specified 30 [pF] is added?
In my opinion, the slope of the voltage rise / fall of the FBK input becomes smaller, and the graph of load capacitance and delay difference specified in the application note is no longer in a linear relationship.
(Therefore, the amount of delay with respect to the load capacity varies greatly from component to component).
However, although the variation will be large, I think that the PLL will not be unlocked.
Or, if other behavior (such as PLL lock cannot be guaranteed) is expected, please let me know the behavior.
MPN : CY2308ZXI-1HT
I referred to the information in the link below.
CY2308 Datasheet
https://www.cypress.com/file/38856/download
AN1234 - Understanding Cypress’s Zero Delay Buffers
Best Regards,
Naoaki Morimoto
Show Less