Difference between CLKOUT and CLKx in CY2305SXI-1

[TeMa_2997106]

When the clock input to the REF pin is branched and output as it is, is there any difference in the connection method and usage between the CLKOUT and CLK1-4 pins?

This device has a total of 5 CLK output pins, CLKOUT and CLK1-4. Only CLKOUT has an internal feedback path. Therefore, I would like to know if there are any differences in characteristics from other output pins.

Thanks,
Tetsuo

[PradiptaB_11 · Accepted solution]

Hi,

The CLKOUT pin differs from the other CLK1-4 output pins with regards to the internal feedback path. . Because the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. Other output pins cannot be used for this purpose and this is the only difference between these pins.

Thanks,

Pradipta.

[TeMa_2997106]

Pradipta-san,

Thank you for your comment.

I'd like to use this IC as a Zero Delay Buffer. Fin is 66.67MHz. The output is 4ch to SDRAM and 1ch to FPGA. The load is 3.5pF for SDRAM and 7pF for FPGA.

In this configuration, is it better to open CLKOUT and connect using only CLK1-4? Or to connect each with CLKOUT and CLK1-4?

Thanks,
Tetsuo

[PradiptaB_11]

Hi Tetsuo-san,

You can connect the clockout to FPGA with 7pf load and clock 1 to 4 to SDRAM with 3.5 pf. Then you can adjust the lead in CLK 1-4 channels by referring to the datasheet and you can achieve zero delay on all the outputs and clokout as well. 

Regards,

Pradipta.

[TeMa_2997106]

Pradipta-san,

Thank you for your answer again.

I can understand.

Tetsuo