CY294xx at VCXO mode issues

[Mitchell_shen]

有一個VCXO Phase Noise 測試問題, 當VC=1/2 VDD時, Phase Noise 測試會有spur產生

而如果避開VC=1/2VDD 就不會.

但是對於VCXO產品, 標準與客戶要求VC=1/2VDD 進行量測基本數據,那麼會有問題的?

請問Cypress 是否有建議的方案, 或後續是否有改善安排?

https://www.cypress.com/documentation/application-notes/an210253-cy294xx-high-performance-clock-gett...

[PradiptaB_11 · Accepted solution]

Hi Mitchell,

There is a spur at Vc = 0.5 VDD in VCXO mode as the application node also points out. Currently there is no solution by configuration and/or external circuitry. Your voltage should be out of the voltage range VDD/2 - 10 mV to VDD/2 + 10 mV.

Thanks,

Pradipta.