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Clocks

NaMo_1534561
New Contributor II

Hello,

I have questions below parameters in CY2308 datasheet.

1) t6 Delay, REF rising edge to FBK rising edge :  max +/-250ps

Please tell me the meaning of this regulation.

I understand that this rule is not the input condition of the clock buffer, but the maximum value of the phase shift between the REF input and the FBK input when the PLL of the clock buffer is synchronized. Is my understanding correct?

(The clock buffer keeps the deviation between the REF input and the FBK input within this value.)

2) CL, Load capacitance, below 100 MHz : max 30pF

Regarding the capacitance to be added to the CLK A1 output returned to the FBK pin, what will happen if a capacitance exceeding the specified 30 [pF] is added?

In my opinion, the slope of the voltage rise / fall of the FBK input becomes smaller, and the graph of load capacitance and delay difference specified in the application note is no longer in a linear relationship.

(Therefore, the amount of delay with respect to the load capacity varies greatly from component to component).

However, although the variation will be large, I think that the PLL will not be unlocked.

Or, if other behavior (such as PLL lock cannot be guaranteed) is expected, please let me know the behavior.

MPN : CY2308ZXI-1HT

I referred to the information in the link below.

CY2308 Datasheet

https://www.cypress.com/file/38856/download

AN1234 - Understanding Cypress’s Zero Delay Buffers

https://www.cypress.com/documentation/application-notes/an1234-understanding-cypress-s-zero-delay-bu...

Best Regards,

Naoaki Morimoto

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi Naoki-san,

Please find our comments below for your questions.

1) Your understanding is correct for the t6 parameter.

2) We have tested the part for a max of 30 pF load capacitance under 100 MHz and a max of 15 pF for over 100 MHz. We cannot guarantee any datasheet listed performance if the device is operated  outside of the operating conditions. Since we have not tested the part we cannot say what will happen or how the device may respond, maybe the linear relationship will be maintained with some affect on the performance or as you say the PLL may lose lock but we cannot say anything with certainty.

Regards,

Pradipta.

View solution in original post

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2 Replies
PradiptaB_11
Moderator
Moderator

Hi Naoki-san,

Please find our comments below for your questions.

1) Your understanding is correct for the t6 parameter.

2) We have tested the part for a max of 30 pF load capacitance under 100 MHz and a max of 15 pF for over 100 MHz. We cannot guarantee any datasheet listed performance if the device is operated  outside of the operating conditions. Since we have not tested the part we cannot say what will happen or how the device may respond, maybe the linear relationship will be maintained with some affect on the performance or as you say the PLL may lose lock but we cannot say anything with certainty.

Regards,

Pradipta.

View solution in original post

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NaMo_1534561
New Contributor II

Hello Pradipta-san,

Thank you for your answer.

My question has been cleared, so this case is closed.

Best Regards,

Naoaki Morimoto

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