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Clocks

kaquc_2151576
New Contributor

As a follow on to this closed discussion: https://community.cypress.com/message/187923

We’ve tried put ferrite beads, but it made the ripples worse, the aurora eye still close. We’ve built a brand new PWB board with CY2304SXI-2, so there is no need to rework, but the aurora eye still close. We are just wondering that why CY2304SXI-2 doesn’t perform like CY7B991V-5JXI, it is because CY2304SXI-2 has more jitter? It that possible you guys can send a technician to our lab for debugging?

This table is the test result for the old PWB board (it needs to rework in order to drop CY2304SXI into CY7B991V-5JXI footprint)

Aurora Eye

Other functions

Input support

CY7B991V-5JX

Open

Work

LVTTL

CY2304SXI-2

Close

Work

TTL

CY2304SXI-1

Close

Work

TTL

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3 Replies
PradiptaB_11
Moderator
Moderator

Hi Quan,

Can you let us know all the requirements for your application. Like can you let us know the jitter requirement for the device for this application.

Can you share with us the schematics for the clock part.

Thanks,

Pradipta.

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kaquc_2151576
New Contributor

The output pk to pk jitter requirement for the device(CY2304SXI-2) is less than 400ps, but the measurement at output of CY2304SXI-2 was more than 500ps

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Capture.JPG

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PradiptaB_11
Moderator
Moderator

Hi Quan,

In the schematic, can you may  remove “filter for input”: 274-ohms and 180pF. This will slow the edge which can lead to worse jitter.

Another point is output series resistor: 49.9-ohms, we think your trace is ~50ohms, it might cause the over dumped in impedance matching. If possible can we get the scope shot for the output. Can you implement these changes and check once. The drive characteristics are different for CY2304 and ROBO part and hence we need to modify the schematics.

Thanks,

Pradipta.

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