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Should the connection to FBIN be taken into account as the load to the output pins?
For example, if FBIN is derived from OUT2, can OUT2 also be used to connect directly to another component, e.g. an ADC clock input?
If this load is acceptable, would this affect zero input-output delay performance?
Should instead use a 1:2 fanout buffer from OUT2 and from it fanout to FBIN and the ADC?
Thank you for making the time to answer!
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Clock Buffers
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- CY2302
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Hi,
We will suggest you to use the fan out buffer instead of directly connecting OUT2 to ADC and FBIN. Otherwise the loading will need to be taken into account.
Thanks,
Pradipta.
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Hi,
We will suggest you to use the fan out buffer instead of directly connecting OUT2 to ADC and FBIN. Otherwise the loading will need to be taken into account.
Thanks,
Pradipta.
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@PradiptaB_11 Followup question:
I am curious, is this because that would exceed the driving capability of the output, or because the additional load would have some impact on zero delay performance?
At lower frequencies, when about 1ns delay is tolerable, would be OUT2 able to drive FBIN and another LVCMOS part?
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Hi,
The additional load will impact the ZD performance and if load exceeds the driving capability of the output it can result in the device being damaged.
It is a general suggestion to use the fan out buffer. If say we do not use we will get a delay depending on the different loading conditions of OUT1 and OUT2. If that delay is tolerable to the user then there is no issue.
Thanks,
Pradipta.