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Clocks

GrBa_3991371
New Contributor

I am having a problem in production where the frequency output of the CY2291 is outside previously established tolerances.  I am trying to calculate what the realistic tolerances should be following the discussion in https://www.cypress.com/file/42656/download.  In order to do this, I need to know the process variation and voltage/temperature stability of the CY2291 (this is not listed in the datasheet).  Can anybody provide these numbers?

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PradiptaB_11
Moderator
Moderator

Hi Greg,

The crystal you are using has a frequency tolerance of 20 ppm and temperature stability of 50 ppm as mentioned by you. For worst case our device can have internal Capacitance of 16.15 which takes the the limit to 37 ppm as mentioned by you and temperature stability as mentioned is 5 ppm. So total error which can be induced will be 112 ppm.

Thanks,

Pradipta.

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PradiptaB_11
Moderator
Moderator

Hi,

Can you provide us with more details on this. What is expected output, what is the output you get. Can you share the schematics with us. How many devices are sowing this behavior.

Thanks and Regards,

Pradipta.

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GrBa_3991371
New Contributor

Hi Pradipta,

Sure - the schematic is shown below.  Out of a batch of 165, about 25 are out.  However, I believe the tolerances to be too tight.  They are currently set as follows:

  • 16 MHz ± 320 Hz (± 20 ppm, or 0.002% tolerance)
  • 24 MHz ± 480 Hz (± 20 ppm, or 0.002% tolerance)
  • 32 MHz ± 640 Hz (± 20 ppm, or 0.002% tolerance)

Given the crystal specs of ±20ppm for frequency and ±50ppm for temperature stability, this seems too tight, but I need to know what to factor in for the CY2291 to come up with a good tolerance.

Thanks,

Greg

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PradiptaB_11
Moderator
Moderator

Hi Greg,

I talked to our product expert for the device also. Do you observe any lot dependency in failures ?

The overall comment is that the requirement you consider 20 ppm is impossible for us because you are using crystal with 20 ppm tolerance and 50 ppm for temperature tolerance total 70 ppm this is out of the requirement and no margin is left for the device.

Also, CY2291 internal Cap is targeted 34 pF, thus 17 pF crystal is recommended. Since this internal Cap is made of Silicon we can roughly estimate the value may vary by 5 % (max) so that CL as seen from the crystal may be 16.15~17.85 pF.

The document that you have referenced describes the tolerance of 2291 is 20 ppm. This means the TS parameter (of the Crystal) would be ~20 ppm/pF (reasonable value).

This is all that we can provide you with as we don't have any design/char/statistical document for this.

Thanks,

Pradipta.

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GrBa_3991371
New Contributor

Hi Pradipta,

Thank you for your reply.  Since we're using a crystal that is 18pF and the worst-case silicon capacitance is 16.15pF, we should say 37ppm for the chip.  What about the "Voltage and Temperature stability" of the chip?  The document lists 5ppm as a typical; does that seem reasonable?  So for the chip as a whole, I should use 42ppm in total, correct?

Thanks,

Greg

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GrBa_3991371
New Contributor

Hi Pradipta,

Please confirm the tolerance range sounds reasonable so I can release my documentation.

Thanks,

Greg

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PradiptaB_11
Moderator
Moderator

Hi Greg,

The crystal you are using has a frequency tolerance of 20 ppm and temperature stability of 50 ppm as mentioned by you. For worst case our device can have internal Capacitance of 16.15 which takes the the limit to 37 ppm as mentioned by you and temperature stability as mentioned is 5 ppm. So total error which can be induced will be 112 ppm.

Thanks,

Pradipta.

View solution in original post

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