There are weak pull-down for REF input and all outputs of Cypress clock buffers that can be checked in respective datasheets. One do not need to provide pull-downs, but if really needed, 5K or 10K can be fine. The lower the resistor value, the strong it will pull. In cases where the input frequency drops below about 2 MHz, the PLL powers down and the outputs are tri-stated. In this case, the outputs are pulled low by these pull down resistors to provide a known state.
