About the output CLK_P and CLK_N for CY29411

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NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

Hello

I wrote data in I2C using PSOC in CY29411, but no signal was output from either CLK_P or CLK_N.Please refer to the attachment for details including questions.

Q1) Please tell me why there is no clock out from CLK_P and CLK_N?

Q2) When the information of only the setting written in the JEDEC File is written to CY29411 by PSOC I2C, is the CLK output automatically started? Or is there any other settings to start CLKs?

Best Regards

Arai

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1 Solution

Sorry for the late response.

For your questions, please see the following comments.

---------------------------------------------------

Q1)Can I consider all registers written by I2C below?

Register Address: 0x10 ~ 15, 0x20 ~ 25, 0x30 ~ 35, 0x40 ~ 45, 0x50 ~ 57

Answer: For CY29411, customer can write the following address: 0x10~0x15(FS0),0x50-0x57(Common configurations), 0xD4~0xD6(user configurable information, free to write, not effect to the device functionality).

Q2)Also, does the CLK_P, N output come out unless the operation called "Loop Lock" shown in Fig. 3 of CY2941x / CY2942x datasheet 002-03966 Rev. * C is performed?

Answer:User will see the output when state machine in the device gets “Active” state. in order to move the state from “Command Wait” to “Active”, it needs the procedures that described in section 5 programming interface in AN210253. Otherwise, we can’t guarantee the behavior of the device.

Q3)Also, what kind of operation "Loop Lock" is specifically in I2C Should I set it?

Answer: The “Loop Lock” command is shown below:

text.png

------------------------------------------------------

If I was correct, customer was using the blank part of CY29411.

For the blank part, the device will enter “command wait state” when power is on.

Customer needs to write the configuration data into the device and issue some specific commands so that the device could output the clock signal.

There are two ways to get output from the device: “functional programming” and “eFuse programming”.

“Functional programming” will get output without programming the eFuse-OTP-, the setting will be loss when power is down.

“eFuse programming” will write the configuration data into the device OTP area permanently.

The program routines for these two programming method are shown below:

Capture.PNG

For more details, please refer to section 5 programming interface in AN210253 - CY294xx High-Performance Clock: Getting Started and Best Design Practices.

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5 Replies
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Arai-san,

A1) Did the I2C packages being send successfully?

A2) Was OE pin enabled?

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NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

Hello RuzheZ-san

>A1) Did the I2C packages being send successfully

Could you please tell me more details mentioned above? What should I check for I2C packages?

After sending the JEDEC File data by PSOC with I2C, is it ok to output  automatically?

Best Regards

Arai

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Hello Arai-san,

Are there ACK signals when sending the I2C command?

Yes. After I2C command sent successfully, the chip should output clock.

Best Regards,

Ryan

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NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

Hello Ryan san

>Are there ACK signals when sending the I2C command?

➡ Yes, ACK response has been confirmed.I will attach the communication waveform below.This waveform is when Slave Address: 0x55, Data: 0xAA is written to Register @ Address: 0xD4, and the register is read immediately.

ACK and NACK are occurring correctly.

(Reading also returns write data correctly)

I2C_Wave_20200108_2.bmp

>Was OE pin enabled?

➡ Yes

Q1)

Can I consider all registers written by I2C below?

Register Address: 0x10 ~ 15, 0x20 ~ 25, 0x30 ~ 35, 0x40 ~ 45, 0x50 ~ 57

Q2)

Also, does the CLK_P, N output come out unless the operation called "Loop Lock" shown in Fig. 3 of CY2941x / CY2942x datasheet 002-03966 Rev. * C is performed?

Q3)

Also, what kind of operation "Loop Lock" is specifically in I2C Should I set it?

LoopLock.png

Best Regards

Arai

0 Likes

Sorry for the late response.

For your questions, please see the following comments.

---------------------------------------------------

Q1)Can I consider all registers written by I2C below?

Register Address: 0x10 ~ 15, 0x20 ~ 25, 0x30 ~ 35, 0x40 ~ 45, 0x50 ~ 57

Answer: For CY29411, customer can write the following address: 0x10~0x15(FS0),0x50-0x57(Common configurations), 0xD4~0xD6(user configurable information, free to write, not effect to the device functionality).

Q2)Also, does the CLK_P, N output come out unless the operation called "Loop Lock" shown in Fig. 3 of CY2941x / CY2942x datasheet 002-03966 Rev. * C is performed?

Answer:User will see the output when state machine in the device gets “Active” state. in order to move the state from “Command Wait” to “Active”, it needs the procedures that described in section 5 programming interface in AN210253. Otherwise, we can’t guarantee the behavior of the device.

Q3)Also, what kind of operation "Loop Lock" is specifically in I2C Should I set it?

Answer: The “Loop Lock” command is shown below:

text.png

------------------------------------------------------

If I was correct, customer was using the blank part of CY29411.

For the blank part, the device will enter “command wait state” when power is on.

Customer needs to write the configuration data into the device and issue some specific commands so that the device could output the clock signal.

There are two ways to get output from the device: “functional programming” and “eFuse programming”.

“Functional programming” will get output without programming the eFuse-OTP-, the setting will be loss when power is down.

“eFuse programming” will write the configuration data into the device OTP area permanently.

The program routines for these two programming method are shown below:

Capture.PNG

For more details, please refer to section 5 programming interface in AN210253 - CY294xx High-Performance Clock: Getting Started and Best Design Practices.

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