Traveo II
Discussion forum regarding 32-bit Traveo™ II Microcontroller - based on ARM® for automotive body electronics applications; cutting-edge performance, safety, and security features topics.
Discussion forum regarding 32-bit Traveo™ II Microcontroller - based on ARM® for automotive body electronics applications; cutting-edge performance, safety, and security features topics.
Hi. I have a problem with uController CY96F315R. I use CAN and pin P3.0 as input for SENT interface. When I set register PIER3 pin 0 as input and there are pulses on this pin - uController hangs up in several time, if i use pin P2.4 for the same purposes I have no any problems. It is no mention initialize any other periphery or no. I used ONLY PIER3.0 and CAN and only one interrupt (CAN). I tryed to found out where Controler hangs up but it is very different part of program, there is no regularity.
Simple code:
void main(void)
{
DDR02_D22 = 1; // Init Wdt
DDR02_D25 = 1; // Power on
PDR02_P5 = 0;
PIER03_IE0 = 1;
PIER03_IE2 = 1;
while (1)
{
PDR02_P2 = 1; // Feeding Wdt
PDR02_P2 = 0; // Feeding Wdt
}
}
If pulses applied to P3.0 (about 10 kHz) the watchdog resets uC in abou 2 minutes
Show LessLast year I asked where I could get Demo project of Traveo 2 Starter Kit (CYTVII-B-E-1M-SK) for IAR.
KiKo_1837836
Level 2
I received the following answer soon.
Hello,
Please kindly get in touch with your Cypress contact window for any demo project or sample code of Traveo II.
Kind Regards,
Yuva
Then I asked the same question to Japanese Cypress Agency (HAKUTO).
But he says that NDA is necessary.
If you still need the demo project, please ask again to CYPRESS DEVELOPER COMMUNITY.
Could you please kindly advise me where I could get a simple demo project file (.eww) for IAR Workbench.
Best regards.
KiKo
Show LessTraveo II CYT4B can run on 350MHZ? code is as follow:
#if (CY_SYS_PLL400M_0_FREQ == CY_SYS_PLL400M_0_350MHz)
// PLL_OUT = 24,000,000(Feco) / 3 * 125 / 5 = 200,000,000Hz
// Restriction: 400,000,000 <= Fvco <= 800,000,000
// This time, Fvco = 16,000,000 * 175 / 4 = 700,000,000.
#define CY_SYSTEM_PLL0_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (175UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (6UL)
/*
#define CY_SYSTEM_PLL0_CONFIG_REFDIV (3UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (125UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (5UL)
*/
#elif (CY_SYS_PLL400M_0_FREQ == CY_SYS_PLL400M_0_320MHz)
Dears.
Now I’m taking the test with software logic analysis of Traveo II SDL 6.6.0 on CYTVII-B-E-176-SO.
In UART(115200Baud rate) clock part, I don’t understand the following code to configure the fractional divider.
uint64_t targetFreq = UART_OVERSAMPLING * boadrate; uint64_t sourceFreq_fp5 = ((uint64_t)sourceFreq << 5ull); uint32_t divSetting_fp5 = (uint32_t)(sourceFreq_fp5 / targetFreq); Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_24_5_BIT, 0ul, ((divSetting_fp5 & 0x1FFFFFE0ul) >> 5ul), (divSetting_fp5 & 0x0000001Ful)); |
---|
Could you give me your explanation or tips to clearly understand it?
Br,
WonjinHan.
Show LessNow Making...
--------------------Configuration: IS12.prj - Debug--------------------
InitManage.c
*** .\Driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
*** .\Driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
main.c
*** .\Driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
*** .\Driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
TaskManage.c
*** .\Driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
*** .\Driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
_ffmc16.c
*** d:\work\seat\source\cs95msm\driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
VCT.c
*** d:\work\seat\source\cs95msm\driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
RLT.c
*** d:\work\seat\source\cs95msm\driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
*** d:\work\seat\source\cs95msm\driver\_ffmc16.h(16) E4077P: #error "The I/O register file of the specified CPU option does not exist"
ADC.c
can you tell me why ? thanks! F2MC-16 Family SOFTUNE Workbench V30L35; MB96F646R MCU
Show Less请帮忙确认下TRAVEO II CYT2B9/CYT2B7 系列 晶元产地以及封测地信息,尽量详细,谢谢
Hello Community,
I'm reading this document:
Microsoft Word - mcu-an-300213-e-v13-16fx_flash_security.doc (fujitsu.com)
In section 2.1 the document sais:
'[...] If the supplied Unlock Key is all 0, the Flash Security cannot be disabled at all.'
My question is: If I set the Unlock Key fully with zeros, then will I be able to perform a Chip Erase with the CYPRESS FLASH MCU Programmer after this full-zero setting is applied?
Thank in advance,
Gabor
Show LessHi, I am about to connect a Touchscreen which uses CYTMA568 through I2C to a custom carrier board with NXP iMX6 Application processor.
The linux is built with openembedded / yocto project (dunfell branch) and uses a customized device tree.
First, the BSP provided by the SoM Manufacturer (Toradex, SoM is Colibri iMX6DL), didn't provide support for this touch controller.
I found the following patch series to add the driver:
https://lwn.net/ml/linux-kernel/20180703094309.18514-1-mylene.josserand@bootlin.com/
I also added a node in device-tree according to the binding documentation like this:
&i2c3 {
status = "okay";
[...]
cyttsp: cyttsp@24 {
compatible = "cypress,cyttsp5";
reg = <0x24>;
interrupt-parent = <&gpio7>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
status = "okay";
};
};
I get the following errors during boot:
[ 0.394465] cyttsp5 1-0024: Error on deassert int r=-22
[ 0.399802] cyttsp5 1-0024: Fail initial startup r=-19
I can use i2cdetect and i2cread to access the device, but the touch driver isn't loaded properly.
Show Less
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