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I have fast data >200Mbps to be sent out to a Wifi access point.

The protocol of this fast data is SLVS.  So I would use an FPGA to convert from SLVS to USB2.0.

This FPGA shall then be interfaced to the CYW54907 USB2.0 port and transmitted over Wifi.

1) Do you see any issue with this setup configuration to the USB2.0 port of the CYW54907?

2) What is the typical throughput speed will I expect going from USB2.0 to Wifi over the air (assume the environment is clean from other radio sources)?    Will I be able to reach >200Mbps over the air with the CYW54907?

Trying to get the Phoenix RLC tester project up and running.

Cannot find the component project file.

Regards, Dana.

Eclipse IDE for ModusToolbox Version: 2.2.0 Build ID: 2181 CY8CPROTO-062-4343W KitProg3

I've been developing code using FreeRTOS for several months now, and suddenly the debug environment shuts down after programming my application.  No error mesages. I've tried undoing my changes, and the problem still occurs.  

srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : SWD DPIDR 0x6ba02477
shutdown command invoked
Info : psoc6.dap: powering down debug domain..

Program runs without pausing at start of main().  Runs as expected. I just can't debug it (no breakpoints, etc).

Problem doesn't occur with Hello World app.

Full capture:

Christian

I designed a PCB that uses the CYPD3177 for both negotiating 9V at 2A minumum and convert the voltage down to 5V via a buck converter, but which also uses the SAFE_PWR_EN as described in your schematic / documentation using two P channel mosfets to connect VBUS with 5V OUT in the case that the USB PD negotiations fail - in which case the 5V could still power my system in a low power mode.
However: for some reason the SAFE_PWR_EN pin is high (5V), when the system is connected to a regular USB power source (tested both with a USB A power adapter and a MacBook Pro via its USB-C port). But this means the mosfet stays disconnected and 5V OUT is not powered - which is the exact opposite behavior then what I expected. Expected was the SAFE_PWR_EN being pulled low, which then makes the P channel mosfets connect VBUS to 5V OUT.
Why is SAFE_PWR_EN high (5V) when a 5V source is connected and not low?
How do I fix this and make sure VBUS is connected to 5V OUT, when the USB PD negotiations fail?

I'm currently investigating the S70FL01GSAG 1Gb device as a replacement for the S25FL512S 512Mb device due to a larger flash capacity requirement. While trying to compare the two datasheets, it seems the S70FL01GSAG does not include much information regarding the device registers. Does the register information for S70FL01GSAG, similar to what is shown in the S25FL512S datasheet, exist anywhere and if so can someone provide me with it?

Dear community members

I need to measure the temperature of an FF800R12KE7 IGBT with an NTC sensor. I would like to know what is the best position to place the sensor. I tried around it but the temperature varied a lot with the position of the sensor. I plan to place it below the IGBT. But I wouldn't know which side would be better or if the ideal is right in the middle.

Kind regards,

Hi there,

Can you confirm whether the statement below is true?

"Where a watchdog timeout alarm (CPU or safety) is triggered the microcontroller will always reset"

I am learning about recovery timers and so far through my observation this appears to be true. I find the wording in the manual ambiguous however, where the word "ensure" is used in reference to this.

Thanks

HI,

We were testing the BLE functionality with Android9 OS.

During testing we found that BLE connection failed with the error showing  "bt_smp : dhkey chcks do no match".

This is random issue and observed during paring and unpairing. while performing this exercise we observed the dhkey mismatch error after 10 iteration of paring and unpairing..

Could please help on this.

Thanks,

Rajendra 

Hello Experts,

I am referring this document (page 36) for my configuration of UART to 115200 baudrate. I am not getting desired output on my putty terminal(I can see continuous junk getting displayed)

https://www.infineon.com/dgdl/Infineon-AN225401_How_to_Use_Serial_Communications_Block_(SCB)_in_Traveo_II_Family-ApplicationNotes-v05_00-EN.pdf?fileId=8ac78c8c7cdc391c017d0d3e657867d2

FYI.. This is my Cy_SysClk_PeriphSetFracDivider function settings.

CLK_PERI Frequency external crystal = 20MHz
115200(baud rate) * 16(OVS) = Input Clock = 1843200 Hz

DIV24.5 = 20MHz / 1843200 = 10.8506

Fractional Divider
Integer : 10 , Fractional : 27 (0.8437 = 27/32)

I have one basic doubt is CLK_PERI freq is same as external crystal oscil(ECO)