Hi,
We plan to use the FX3 GPIF II to drive a Xilinx Kintex-7 SelectMap programming interface.
In order to control it properly, we'd like to write/read PROG_B, INIT_B and DONE to/from GPIOs controlled by firmware and use GPIF II just for clock, data and CSI_B.
In fact, we just have to init sequence by firmware with PROG_B/INIT_B then wait for a data in a socket, then send it on the GPIF II data bus and assert CSI_B in the same time data is valid, until there is no more data and DONE pin is driven high.
As the GPIF state machine will rely only on data present in the socket, it should be very simple like that:
IDLE -> Set data on bus -> Hold data on bus to respect FPGA setup/hold requirements -> IDLE ->....
But, what should be the transition trigger from IDLE to Set data on bus? Since it does only depends on data present in the socket? Is DMA_RDY_CT ok? Because it tells DMA is ready, not if a data is present in the socket...
Thanks in advance for the help.
Johan
