GPIF control out hold time?

[Anonymous]

 The data sheet specifies a tCTLO (clock to out valid) time of 8ns and a tCOH (clock to out hold) of 0ns.  If this is true then there aren't many devcies that will interface with the CYUSB3014 including another CYUSB3014 or a high speed synchronus FIFO which both require 0.5ns of hold time on a control input.  In my case the CYUSB3014 will be the GPIF master and driving the clock and controls.

   

I'm looking for clarification of this timing spec.

       

Thanks, Bill

[Anonymous]

 Hi Bill,

   

Yes, you are right.

   

Could you please let me know the interface that you are trying with FX3? What is the external processor?

   

-PRJI

[Anonymous]

 Two devices actually, an Altera Cyclone IV and a very large IDT SuperSync FIFO.  Like the FX3 the FIFO has a setup time of 2ns and a hold time of 0.5ns on the control signals.  The interface to the FIFO is on the write side of the FIFO so the write enable being produced by the FX3 is the signal I have concern about.  I'm working with Altera on simulation issues with the Altera FPGA but it appears from the Altera tools that I may be able to meet the timing with that device but that is not what simulation is telling me, thus Altera's involvement.  The interface to the IDT FIFO is on the write side of the FIFO.  The interface to the FPGA is both read and write as there are numerous control registers and another smaller FIFO that the FX3 will be reading from.  So you see the synchronous FIFO mode of the GPIF interface is not a workable solution in this case as we are moving data in both directions and also need the register read/write access including address to point to the proper register.  The only processor on the module will be the ARM in the FX3.

[Anonymous]

Hi Bill,

   

The hold time from opposite clock edge is about 1/2 of clock period.

   

br,

   

kalev

       

[Anonymous]

 Hi,

   

I would suggest you to adjust the control signal asserted time in the state machine.

   

-PRJI