Build error E2071, but no details in the report file

[Anonymous]

Hello,

   

we are beginners in the PSOC5 programming. We tried to build a system with some communication interfaces (USB, UART, SPIO, I2C) but it seemed that the PSOC5 is too small. We cant locate the error in the report file.

   

We used "PSoC Creator  2.2 Component Pack 5 (2.2.0.293)".

   

The device was "CY8C5868AXI-LP032".

       

Thank you for the help

   

---------------------------------------------------------------------------------------

   

.....

   

Analog Placement ...
Log: apr.M0058: The analog placement iterative improvement is 26% done. (App=cydsfit)
Log: apr.M0058: The analog placement iterative improvement is 55% done. (App=cydsfit)
Analog Routing ...
Analog Code Generation ...
Digital Placement ...
Error: plm.M0046: E2071: The design requires 25 UDB(s) but the device has 24. See the report file for details.
Error: plm.M0046: E2055: An error occurred during placement of the design.
Error: plm.M0046: "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin/sjplacer.exe" failed (0x0000000B)
Dependency Generation ...
Clean Temporary Files ...
Error: cdf.M0005: CyDsFit aborted due to errors, please address all errors and rerun CyDsFit. (App=cydsfit)
--------------- Rebuild Failed: 03/23/2013 17:21:33 ---------------
 

       

------------ our results in test04.rpt

   

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital domain clock dividers :    7 :    1 :    8 :  87.50%
Analog domain clock dividers  :    1 :    3 :    4 :  25.00%
Pins                          :   64 :    8 :   72 :  88.89%
UDB Macrocells                :  153 :   39 :  192 :  79.69%
UDB Unique Pterms             :  321 :   63 :  384 :  83.59%
UDB Total Pterms              :  358 :      :      :
UDB Datapath Cells            :   21 :    3 :   24 :  87.50%
UDB Status Cells              :   19 :    5 :   24 :  79.17%
             Status Registers :    3
            StatusI Registers :   14
                   Sync Cells :    8 (in 2 status cells)
UDB Control Cells             :   17 :    7 :   24 :  70.83%
            Control Registers :   12
                 Count7 Cells :    5
DMA Channels                  :    0 :   24 :   24 :   0.00%
Interrupts                    :   10 :   22 :   32 :  31.25%
DSM Fixed Blocks              :    1 :    0 :    1 : 100.00%
VIDAC Fixed Blocks            :    0 :    4 :    4 :   0.00%
SC Fixed Blocks               :    0 :    4 :    4 :   0.00%
Comparator Fixed Blocks       :    0 :    4 :    4 :   0.00%
Opamp Fixed Blocks            :    0 :    4 :    4 :   0.00%
CapSense Buffers              :    0 :    2 :    2 :   0.00%
Decimator Fixed Blocks        :    1 :    0 :    1 : 100.00%
I2C Fixed Blocks              :    1 :    0 :    1 : 100.00%
Timer Fixed Blocks            :    4 :    0 :    4 : 100.00%
DFB Fixed Blocks              :    0 :    1 :    1 :   0.00%
USB Fixed Blocks              :    1 :    0 :    1 : 100.00%
LCD Fixed Blocks              :    0 :    1 :    1 :   0.00%
EMIF Fixed Blocks             :    0 :    1 :    1 :   0.00%
LPF Fixed Blocks              :    0 :    2 :    2 :   0.00%
SAR Fixed Blocks              :    0 :    2 :    2 :   0.00%
 

[Bob_Marlowe]

As usual: First cut goes deepest, the error is explained as

   

Error: plm.M0046: E2071: The design requires 25 UDB(s) but the device has 24. See the report file for details.

   

Afaik there is no PSoC devive with more than 24 UDBs, sou you'll have to shrink your design or use 2 PSoCs to get everything you need onto your board.

       

Bob

[Anonymous]

Hello,

   

thank for the quick answer.

   

I have no idea what part of my design causes the "overflow" in detail and I hoped that the error report gave me some more information about the error. When I remove a SPI interface from my design then the build success.

   

When I simple add the SPI resources to my design I think I don't reach the limits ?

   

Datapath Cells 1

   

Macro cells 12

   

Status Cells 1

   

Control Cells – 2

[Bob_Marlowe]

There is not one component that blows your design, it is the sum of all components together.

   

Check for each usermodule if a fixed function is offered and the restrictions implied by using the fixed-function implementation is sufficent for your design. So you might overcome your shortcoming (smile)

       

Bob

[Anonymous]

One thing you can do is to change some hardware such as I2C from UDB type to Fixed function type.
You can also check the data sheet of the components and change configuration that use less UDB resources.
Say if you only need to transmit message out, then you only need a TX option of UART not a TX+RX UART...
 

[ETRO_SSN583]

Consider posting your design so forum can take a look at it.

       

Regards, Dana.