5 Replies Latest reply on Mar 27, 2013 2:30 AM by gaya

    Endpoint Pinout mapping on CY3684

    alan.scott

      Could someone point me to an endpoint to P1 - P6 mapping on the CY3684?

         

      I have the default/alternate pin configurations from the schematic and chip documentation but can't seem to find how they are mapped to endpoints.

         

      I had thought it was Endpoint1 to P1, etc but that isn't the case.

         

      Thanks

        • 1. Re: Endpoint Pinout mapping on CY3684
          nikhil.naik

           It is not that way mapped that way.

             

          Please go through chapters 8, 9 & 10 of FX2LP Technical reference manual (TRM) to get an idea of how the endpoint buffers are accessed.

             

          The TRM will be available at the following path after FX2LP DVK installation: C:\Cypress\CY3684_EZ-USB_FX2LP_DVK\1.0\Documentation

             

           

             

          Thanks

             

          Nikhil

          • 2. Re: Endpoint Pinout mapping on CY3684
            gaya

             Hi,

               

             

               

            What did you mean by P1-P6? Please clarify the same? Endpoint is nothing but a buffer in the device, which acts as source or sink of data.

               

             

               

            Regards,

               

            Gayathri

            • 3. Re: Endpoint Pinout mapping on CY3684
              alan.scott
                  "What did you mean by P1-P6? Please clarify the same? Endpoint is nothing but a buffer in the device, which acts as source or sink of data."   
                 
                      
                 
                  The Cypress FX2LP CY3684 Development Board has x6 20pin headers labeled P1 through P6.    
                 
                  The CY3684 EZ-USB FX2LP Development Kit Quick Start Guide these are referenced as GPIO Headers (please see attached picture).    
                 
                      
                 
                  The pinouts on the headers include:   
                 
                      
                 
                   P1 - PB[7:0] / FD[7:0]   
                 
                   P1 - PD[7:0] / FD[15:8]   
                 
                   P2 - PA[7:0]   
                 
                   P3 - PC[7:0]   
                 
                   P4 - D0[7:0]   
                 
                   P5 - A0[7:0]   
                 
                   P6 - PE[7:0]   
                 
                      
                 
                  My confusion is that it looks like PA, PC, D0, PE could be used with an endpoint.   
                 
                  These pins exist on the CY7C68013A family of chips.   
                 
                      
                 
                  Table 9-2 in the TRM shows that only one endpoint can be used with pins FD[15:0] and selected with FIFOADR pins on P2 (pins 14 and 15).   
                 
                      
                 
                  So my questions are:   
                 
                      
                 
                  Is it not possible to map an endpoint to any of the other pins such as PA, PC, D0, PE ?   
                 
                      
                 
                  If not with an endpoint, how does one utilize PA, PC, D0, A0, PE ?   
                 
                      
                 
                  Other documentation (example: AN58069) shows using PB[7:0] rather than the documented alternate name FD[7:0].   
                 
                  Is there no difference between PB,PD and FD[15:0] pins?   
              • 4. Re: Endpoint Pinout mapping on CY3684
                rama.sai.krishna.vakkantula

                Please find answers to your questions in line:

                   

                 

                   

                Is it not possible to map an endpoint to any of the other pins such as PA, PC, D0, PE ?

                   

                          We don't map an endpoint to any of the port pins. We just mention the endpoint details in the descriptor file. If host PC sends some data to endpoint then that data will be written to the endpoint buffer over USB D+ and D- lines. You don't need to map any port pins to endpoint.

                   

                 

                   

                If not with an endpoint, how does one utilize PA, PC, D0, A0, PE ?

                   

                I am explaining you the usage of these port pins by assuming that you need to interface an external device  (let say FPGA) to FX2LP. Then you can interface FPGA to Slave FIFO interface of FX2LP.

                   

                          In Slave FIFO mode, Port A has a mix of fixed function pins for the Slave FIFO interface and alternate functions.

                   

                          In Slave FIFO mode, Port B is defined as the lower 8 bits of the FIFO data bus FD[7:0] and Port D is defined as the upper 8 bits of the FIFO data bus FD[15:8] if bus is set to be WORDWIDE.

                   

                          In Slave FIFO mode, Port C can be used as general purpose IO.

                   

                          Port E definition is determined mainly by the PORTECFG register.

                   

                        •          A0 and D0 are needed if you are going to add an external SRAM to FX2LP. (This is required only if the image (hex) file size is more than 16KB).

                   

                 

                   

                 

                   

                Other documentation (example: AN58069) shows using PB[7:0] rather than the documented alternate name FD[7:0].

                   

                Is there no difference between PB,PD and FD[15:0] pins?

                   

                          No difference. They are data lines in both Slave FIFO and GPIF mode. You can use them as GPIOs if you are not interfacing anything to FX2LP.

                   

                 

                   

                Thanks,

                   

                Sai Krishna.

                • 5. Re: Endpoint Pinout mapping on CY3684
                  gaya

                   Hi,

                     

                   

                     

                  Check it out if you find this useful: http://www.cypress.com/?rID=12926.

                     

                   

                     

                  Regards,

                     

                  Gayathri