How does CY7C68001 and its external master get to realize that there is an IN request from a host PC?

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Anonymous
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        Hello all: When I read the datasheet of CY7C68001, I find that there are SETUP and FLAG interrupts to notify the external master a control transaction vis EP0 and an OUT transaction vis EP68 respectively. But there is no such interrupt signal for an IN transaction. For example, on the cypress USB console, if I select EP6 and enter non data byte, after i click the transfer button, how could the USB chip get to know the request and response accordingly?   
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Anonymous
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 Hi,

   

 

   

I believe you are asking whenever host is sending IN request for data, how does SX2 get notified of this? That will be taken care of by the SIE. If there is data in the USB domain, ready for an IN transfer, then if the host requests for data, it will be sent by the SIE in the data phase. If there is no data at the arrival of IN token, then SIE will NAK the request. Devcie just needs to commit the data to the USB domain; so that whenever host requests for it, it would be sent across by the SIE.

   

 

   

Regards,

   

Gayathri

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Anonymous
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        Dear Gayathri, thank you very much for your reply, it is realy helpful! Thanks again!   
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Anonymous
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 You are welcome

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