GPIF design with master mode to implement 8080 interface

[Anonymous]

Hi,

       

I'm design a bridge to read/write 8080 type device through USB. But I have problem on the GPIF2 waveform design. For write operation, I can use DMA_RDY_CT to trigger write operation. But how to trigger read operation?

   

A sample project that uses GPIF2 as master to interface with a SRAM type device would be much appreciated.

       

Thanks!

   

Rover

[Anonymous]

Hi,

       

Currently we do not have an example with FX3 IN master mode interfaced to SRm. We have developed a FX3 back to back example, with one FX3 in master mode and the other in slave mode. PFA the same.

       

Regards,

   

Gayathri

[Anonymous]

PFA

[Anonymous]

Thank Gayathri or the great example. I tried to design the interface I need by GPIFII designer. However, when I simulating the timing, it reported "invalid state machine path". I attach the design here and hope someone could tell me what the problem is. Thanks!

       

Regards,

   

Rover