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Hi,
I'm trying to set different frequency on PIB block. I found that not all dividers are workable when the source is CY_U3P_SYS_CLK. Here are some values that can work.
4(100M)
8(50M)
10(40M)
16(25M)
32(12.5M)
Others, for example, 48, 64, 100, 128, can't work.
Why?
Thanks,
Rover
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Hi Rover,
I just tested these settings and they all work fine. I get the exact expected clock on the PIB block.
Can you please check again?
Regards
Shashank
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Hi Rover,
How do you come to the conclusion that those specific divider values do not work? Are you not able to see a clock on the PCLK pin?
Regards
Shashank
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Hi Shashank,
Thanks for reply. When I use the dividers that I mentioned, the host can't recognize the DVK, no device found in control center, neither output on PCLK pin (I checked on scope).
Regards,
Rover
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Interesting. It works this morning. All values are workable...
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It seems that is due to isDllEnable setting in CyU3PPibClock_t structure. If it's true then most values will fail.