Why does EZI2C need a 60MHz clock?

[HuEl_264296]

My project needs an I2C EEPROM. Rather than use an actual EEPROM chip, I thought I'd just use the PSoC's EZI2C component.

   

I wired it up as you'd expect, using the special I2C0:SCL and I2C0:SDA pins. Data rate 300kbps, 1 address, Primary slave address 0x50, Sub address size 8, Pin connections Any. The PSoC's Master clock was set to 40MHz. The project is empty except for the EZI2C component and its pins. The main() function does nothing (just an empty loop) after setting up the EZI2C component.

   

When the external device tries to read the "EEPROM", I can see on my logic analyser that it's not working properly. It still doesn't work with a 50MHz master clock. However, if I set the master clock to 60MHz, it starts to work. Please see the attached images showing the waveforms.

[HeLi_263931]

It might just be that the component needs too much CPU time for processing. So a slower clock means that it won't finish its stuff soon enough. What do you do during the interrupts?

[HuEl_264296]

No it's not that. It's something bizarre going on. In another project I have the same component, and it's working fine with a 40MHz clock. 

[HeLi_263931]

So what is then the difference between the two projects? Just the strange workspace file? Or can you replicate the problem by creating a new workspace, duplicating the schematic and the source code? If yes - can you post the project?

[Anonymous]

 maybe you changed something inthe clock configuration window. like sources or acuracy %