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In CyLib.h you find
#elif defined(__GNUC__)
#define CyGlobalIntEnable {__asm("CPSIE i");}
#define CyGlobalIntDisable {__asm("CPSID i");}
Bob
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To elaborate on Bob's answer:
CyGlobalIntEnable is a macro that executes the Assembly instruction "CPSIE i", which means "Change Processor State, Interrupt Enable", and the 'i' specifies interrupt IRQs instead of other options. This is an atomic command that writes to the "PRIMASK" (Priority Mask) register, which appears to be a 1-bit register that (as far as I can find) is not memory-addressable (can't view with the debugger). You can read the register value using the function __get_PRIMASK(). Because it's a masking register, a value of 0 enables interrupts and 1 disables them.
Additional details follow:
From random person's Wordpress site (Google search):
Cortex-M3 Interrupt/Exception Control | Embedded Freaks..
“CPSIE I” is a assembly instruction to enable the priority configurable interrupts. Actually, it’s a shortcut to this longer procedure:
asm volatile ("MOVS r0, #0\n\
MSR PRIMASK, r0");
MSR opcode = Move to system coprocessor register from ARM register.
In CyBootAsmRv.s
; uint8 CyEnterCriticalSection(void)
CyEnterCriticalSection FUNCTION
EXPORT CyEnterCriticalSection
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
ENDFUNC
From the PSoC5LP_CY8C58LP Family Datasheet:
PRIMASK: A 1-bit interrupt mask register. When set, it allows
only the nonmaskable interrupt (NMI) and hard fault
exception. All other exceptions and interrupts are
masked.
From cmsis_armcc.h
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}