Frequency calculation

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Anonymous
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Helle everybody,

I am usin cy8c29466 PSOC1 and i want to calculate frequency. I have 50Hz clock palse. And i am gonna input that any port. I want to show frequency measuremant on LCD at port2.

Please don't advice me "ad2283 example" because it is useless. It's half of C and half of assembly and so complicated. I want to calculate it just 1 Timer. Noting else. Timer8 or 16 will be enough. And I want to hear solutions just in C language. Also there are some examples on internet which are using just in designer 4.4 and this is meaningless. I am using designer 5.1.

So if anybody who can help me i will be appraciate.

Please be quick !!

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pushekm_21
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I remember one of my colleague did this example for some customer using PD5.1. Unfortunately, I won't be able to attach zip file over here. Can you please provide me your email address such that I can send it to you via email.

   

 

   

Best regards,

   

Pushek

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Anonymous
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oguzk@meve.com.tr

   

 

   

thanks..

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Anonymous
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 Hi, 

   

I have sent the example project to the above mentioned email. Please find the same.

   

Regards,

   

Keerthi Raj

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Anonymous
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 hi everybody!

   

I am doing the project on measuring frequency by PSoC. you do have examples of this project please send mail to me.

   

thanks!

   

Email: khanhnguyenptit@gmail.com

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ETRO_SSN583
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At the most basic level you need a gate of known width in time,
and a counter that starts counting when gate is active (high),
from a known value (255 8 bit,  65535 16 bit), and stops counting
when gate goes low. You read the value of the counter, subtract
it from start value, and divide by gate period in seconds.

   

16 bit example, .1 sec gate period, f = (65535 – count value) / .1

   

To setup Gate

   

1) Timer, setup for .1 or 1 sec (resolution would be 10 Hz or 1 Hz
respectively). You set up period to be 2X desired gate period, and
compare value 1/2 period, so that high time of compare output =
gate period, low time = gate period.

   

2) Route timer compare out to counter enable.

   

To setup counter

   

1) Route pin, Fin, to counter clock

   

2) Route timer compare out to counter enable

   

Code

   

1) Load counter with its max allowed value, 255 for 8 bit, 65535 for
16 bit

   

2) Start counter

   

3) Enable timer ISR, on terminal count, that means gate is low, counter
not enabled to count

   

3) Start timer

   

When ISR occurs set a flag and return

   

1) If flag true read counter (gate is low so it is not enabling counter)
and compute frequency. Reload counter with its max value.

   

There are other optimizations that can be done, for example stop and reset
timer when ISR occurs so that gate low period is minimized, and measurement
frequency is increased.

   

If the frequencies you are measuring are very low, like less than 1 Hz,
use reciprocal counter technique.

   

Regards Dana.

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Anonymous
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 Dana give some hints to do the project already. Try to come up with your project. post it here for others to help. But you have to do it yourself to learn. 

   

Happy coding

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ETRO_SSN583
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Here is some reference material that may be of interest.

   

 

   

Regards, Dana.

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Anonymous
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 sir, can i interface my light sensor tsl235 directly with CY8CKIT-001 DVK .

   

Suggest me how i can interface my tsl235 with this kit.

   
     Actually my work is to detect light intensity of different laser and measure its frequency and develop a device which is very sensitive. so i m using TSL235 converter for my work.   
   
     i need to do it on PSoC designer. help send me demo sample and if possible code also.   
   
     Thanks   
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Anonymous
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TSL235 is a light sensor with frequency output. You can refer application note AN2283 - PSoC 1 - Measuring frequency 

   

http://www.cypress.com/?rID=2671

   

 

   

I would suggest to use a light sensor with analog output and then do signal processing inside PSoC. You will be able to reduce the system cost. 

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Anonymous
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 what if i m using tsl235. this AN code is perfect for my work

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Anonymous
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You can use AN2283 for measuring sensor output frequency. However, there is not much PSoC value in just measuring the frequency. If you are doing something else also with PSoC, then it is fine. The best thing would be, as I told earlier, to use a simple light sensor and implement analog processing chain along with calibration inside PSoC. This way, you will be able to use the device to its maximum capacity and also reduce the system cost.

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Anonymous
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 ok.

   

that i m considering your point.

   

if i'll go with analog output sensor then can u please help out with system design and coding. 

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Anonymous
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as  i've mentioned my work above..

   

its simply to measure frequency by falling different color of light on tsl235

   

and check its frequency. also i've to show graph b/w wavelength and intensity for particular color of light in LABview

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Anonymous
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Ishu, we can help to resolve any specific issues which you will have during solution development and provide pointers to the already available materials. 

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ETRO_SSN583
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Posted in another of your threads, here again -

   

 

   

www.cypress.com/

   

 

   

Regards, Dana.

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Anonymous
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 @dana

   

why are u subtracting count value from 65535

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ETRO_SSN583
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Counters in PSOC 1 are down counetrs, so you start at max count vakue,

   

2n - 1, and when the gate stops counter you read it and subtract it from max

   

value to get the number of counts recorded.

   

 

   

Regards, Dana.

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Anonymous
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 i am using two counters for measuring freuency, one counter for 1 sec generation, another counter for counting pulses, after every one sec interrupt generate.

   

now the problem is after 1 sec it does not give exact value

   

   

eg.  if i take 10--->10,for 100-->98,for1000--->992,for 10000--->99960

   

why it come like this,plz help?

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Anonymous
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Based on your results -

   

at 10Hz input, you got exactly 10Hz

   

at 100Hz input, you got 98Hz

   

at 1000Hz input, you got 992Hz

   

at 10KHz input, you got 9.996KHz (is this right?)

   

The error is increasing as you increase your input frequency. This is most probably due to the latency in 1sec ISR execution. 

   

 

   

Another method to implement this is to generate a signal of 1Hz and feed it to capture terminal of timer. Give your input signal to be measured to the clock input terminal of timer. Timer will be captured at every rising edge of 1Hz pulse. The difference in captured counts will give you the frequency of the input signal. This method, doesn't involve CPU in capturing the counts. This is taken care by the timer's capture feature.  

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ETRO_SSN583
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A method I use for precise stable measurements -

   

 

   

1) Use 16 bit timer, and coupled with VC1/2/3 develop 2 Hz, and

   

route this to counter enable. So you have a 1 sec enable on the counter.

   

2) Poll gate, compare output, on gate timer in 1)

   

3) If gate low, and a flag counter has not been read, read counter and subtract it from

   

counter max value, then reload counter with its max value. Set the flag counter has been read

   

so no more readings occur while gate low.

   

4) Contune polling gate, If gate high, reset flag counter has been read.

   

5) Loop to 2)

   

 

   

I use an external 24 Mhz clock which is accurate and stable. If you use internal clock

   

that affects accuracy of measurement. Additionally you can do the gate as 5 Hz, or .1 sec

   

high, for faster readings, and scale answer by 10. Or .01 sec gate.........

   

 

   

You can also do this on ISRs, use compare ISR and also route gate to a buffer to get a

   

negative edge ISR. In this case ISRs will not affect accuracy, repeatability, or stability.

   

 

   

Regards, Dana.

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Anonymous
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 thanks for your reply

   

here iam using two counters, one for 1hz,another for counting pulses?

   

now tell me procedure for eliminating errors?

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Anonymous
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 the AN2042 note module design is also used for measurement of light intensity? plz reply

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ETRO_SSN583
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The external precision clock, if you choose it, will control almost all of the errors.

   

 

   

If you choose internal clock, then during production test, you could have a cal routine

   

where you measure a high precision external frequency, and store a correction value. Note this

   

would only be at room temp, unless you add a temp sensor and sweep temperature while under

   

test.

   

 

   

The basic approach, where the gate is supplied to the enable of the counter, external precision

   

clock, results in only a +/- 1 count error. This takes out all the ISR non-predictable latency you were

   

experiencing.

   

 

   

Regards, Dana.

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ETRO_SSN583
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What is the range of frequencies you want to measure, and what accuracy and

   

resolution do you want in your design ?

   

 

   

Regards, Dana.

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Anonymous
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 i want to capture range of visible spectrum.....and it should cover wide dynamic range. 🙂

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ETRO_SSN583
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Irradiance response of detector looks like -

   

   

 

   

So you have ~ 6 decades of range to measure, implies a 24 bit counter.

   

But you have 1 mHz measurement need. Gate would have to be 1 mHz,

   

or time to measure it would be 1000 secs. So reciprocal counter technique

   

makes sense, for the < 10 Hz frequencies, unless you want to wait 1000

   

secs to get low light value.

   

 

   

Or make a counter mode decision based on a gross measurment, from

   

normal gated F counter to reciprocal counter. See attached ap note.

   

 

   

Regards, Dana.

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Anonymous
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 Dana, i now understand the use of using reciprocal counter. how can i design this on PSoC designer. actually m not so much comfortable on this tool. help me out by sending its design sample and one more thing since i m making use of a simple photodiode to detect light levels, so it is imp.to modulate the light using filters to make my design more sensitive so it can detect low level light. plz help me out.

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ETRO_SSN583
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Here is a basic project you can work from. Test F measured is 1.2 Khz, you can change

   

that by changing period and compare value of TestFreq16 in properties by CouponDropDown" id="_GPLITA_0" style="text-decoration:underline" href="https://community.cypress....

   

 

   

Its run on a PSOCeval1, 29466.

   

 

   

This project is a standard freq cntr, not reciprocal. Maybe you can wrok out the reciprocal

   

approach and post for the forum.

   

 

   

Regards Dana.

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Anonymous
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 thank u

   

here what is the use of test frequency16

ETRO_SSN583
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Thats just to generate a test frequency to measure. Or use an external

   

function generator to measure.

   

 

   

Regards, Dana.

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ETRO_SSN583
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I added one change to project, to insure ISR occured from falling edge of

   

gate gen compare output. Also added was a bunch of descriptive stuff about

   

the design.

   

 

   

Regards, Dana.

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ETRO_SSN583
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One last change, update comments in main.c with below to fix

   

some errors I had in project description.

   

 

   

// This frequency counter is enabled by a simple gate, derived from timer compare output.
// Gate is set up as 1 sec high, 1 sec low, or 2 Hertz. The cycle starts as follows -
//
//         1) Counter period, CounterFreq24, is loaded with 0xFFFFFF, eg full count.
//         2) Gate timer compare out, TimerGateGen16, we will call it gate, goes high, enabling counter.
//         3) Counter counts down at Fx rate, until gate goes low.
//      4) Gate compare goes low, compare output set up to generate an interrupt - edge.
//        5) ISR sets a flag, GateLowFlag, returns.
//        6) In main() GateLowFlag flag is tested, if true, tells main() to service counter
//        7) Counter is stopped, read, reloaded with 0xFFFFFF. stopping counter allows the reload to
//           immeadiatly update counter.
//        😎 Value read is subtracted from 0xFFFFFF (16777215), that result is # counts in 1 sec gate = Hertz
//        9) Value converted to string, written to LCD
//       10) GateLowFlag flag is cleared, counter (CounterFreq24) start API is called. Note because gate is still
//         low for 1 sec, it does not start counting right away until gate goes high.
//
// Notes -
//
//        1) ISR causes no latency as it occurs when gate goes low, disabling counter.
//        2) Gate is 1 sec, could be used as 100 mS to speed up, scale by 10 the reading.
//        3) Gate timer is 1 sec high, 1 sec low, for a 2 sec measurement latency. This
//           can be shorted by changing the period, but keeping compare value same, so duty cycle
//            of gate timer increases, eg. gate high time stays same, but low time shortend.
//        4) Accuracy is limited by internal 24 Mhz clk of PSOC. If you want high accuracy
//           use a precision external clock.
//        5) Accuracy is also a f( frequency ), lower freqs = bigger error. Example if input is 10 Hz,
//           Gate is 1 Hz, there is a minimum count error +/- 1 count, so effectively thats +/-
//         10% error at 10 Hz. Reciprocal counter technique can take care of that.
//        6) The ISR is a C ISR. boot.tpl must be modified in the root project directory to
//            implement the jump vector for interrupt. The interrupt comes from last block in gate timer
//         chain, TimerGateGen16, in this case DBB01, so that jump vector must be modified to "ljmp _yourISRname"
//        7) CounterFreq24 is 24 bit frequency counter, TimerGateGen16 is gate source to drive CounterFreq24 enable,
//           TestFreq16 is a 16 bit timer used to generate a test frequency for debug/measurement, you can eliminate
//         it and its associated code. CompnegISRsignal is a Digital Inverter to produce an ISR on TimerGateGen16
//         compare output -edge.
//        😎 If you need the digital block the DigInv uses to generate ISR on TimerGateGen16 compare output - edge
//         then eliminate it. Set TimerGateGen16 interrupt property to interrupt on Tc, Insert into code that
//         services ISR flag (GateLowFlag) a delay to fix fact Tc out ISR triggers before compare out (gate) falls
//         to low (which disables CounterFreq24 from further counting). Delay would be >=1 clk of TimerGateGen16,
//         which for 1 sec gate, is 1 / 5 Khz = 200 uS to make sure gate, hence CounterFreq24, finishes counting.

   

 

   

Regards, Dana.

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Anonymous
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thanks dana

   

how can i find time interval between rising edge of 1pulse to rising edge of 2 pulse?

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ETRO_SSN583
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I described an approach here -

   

 

   

www.cypress.com/

   

 

   

Regards, Dana.

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ETRO_SSN583
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Also if the pulse train is repetitive Tpulse-pulse = 1 / Fpulsetrain.

   

So just measure F and calculate T.

   

 

   

If pulse train non repetitive, see the post I alluded to earlier.

   

 

   

Regards, Dana.

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Anonymous
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 i tried it today ,but this code is not workingin properway,it gives some error

   

input-         ouput

   

10                       10

   

100                98

   

1000           982

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ETRO_SSN583
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If you are using an external signal for measuement, then

   

results consistent with internal clock accuracy, Reading

   

will be as much as 2.5% off. Thats for 100 Hz or greater.

   

 

   

For single digit Hz frequencies, it can be as much as 100%

   

off due to plus or minus 1 count, for a 1Hz gate. Example,

   

if input is 10 Hz, +/- 1 count is 10% error. Thats why

   

reciproccal counter technique needs to be employed.

   

 

   

If you are using internal TestFreq generator I had in project, make sure

   

you are using a revised project I posted, here again.

   

 

   

Regards, Dana.

   

 

   

Regards, Dana.

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Anonymous
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this zip file is not showing any sample project. can u plz mail it on me on my id.

   

its

   

isha.ishu1117@gmail.com

   

 

   

thanxs

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ETRO_SSN583
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Your email address did not work, so here it is again -

   

 

   

Regards, Dana.

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