- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
At least not making it looking much better than your original solution. What you can do:
- draw your two busses
- for each bus, create 7 breakout wires
- assign each breakout wire with the proper bit (0-6)
- then you can connect the breakout wires with each other
I tested this, and the busses still kept their original names.
Correction: I just tried to build this project, and got the error: "CRL and SR are connected and have inconsistent base names".
So this doesn't work, and seems not to be supported. But in the end this makes sense that way - nets need to have consistent names to ensure proper routing.
I would propose you create a bus containing the data lines and th4 clock. Then you can connect only the lines you really need, like you would do in any other schematics editor.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks. It is a pity that I can not assign a common name of several conductors in different bus.
Information for Technical Support:
When i edit bus and has error - error remains even after removal of the bus.
I have to close the project and download it again.
An example of such an error is attached below.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
A very unusual way to get out of this naming-problem could be to write a custom-component and hoping for the optimizer.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
This "persistent error" problem happens not only with busses, but with serveral others too. Sometimes they even persist aver re-opening the project. And there is no way to clear the error list 😞
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
One of the errors you get has to do with connecting an input pin to the output of the status register, same with the control reg.
Control has inputs, Status has outputs...
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
... and connecting more than 1 signal to form a bus does not work within a component, but you may make the connection on the schematic by specifying the signal to be part of the bus. I would suggest you to correct your Input/Output problem and post your resulting project again.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes, that should always work, I never doubted that. But you wanted to connect differently NAMED nets and that will only work with the UserModule-trick.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
i would like to combine a G1a[7:6] and a G1b[2:0] to a G1[4:0] signal. The G1[4:0] signal should be the input to a 5-bit digital comparator. Any idea how to draw this in Creator?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
This looks like a very nice component. I will certainly test this later. For now i have solved my connection problem with a small verilog component....