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Hi,
What is your application. What are you trying to do? Please dscribe a lttile bit about your application.
Regards,
Gayathri
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Hi Gayathri
In my application,the fx3 device acts as a slave and the FPGA continues to write some certain data to the fx3 p-port .I want to transfer these data to the host computer ,so I created a dma channel with two producer sockets and one consumer socket. I use the USB ControlCenter to check if I get the right data ,then I get this
BULK IN transfer
0000 88 FF 88 FF 90 FF 90 FF 98 FF 98 FF A0 FF A0 FF
0010 A8 FF A8 FF B0 FF B0 FF B8 FF B8 FF C0 FF C0 FF
0020 C8 FF C8 FF D0 FF D0 FF D8 FF D8 FF E0 FF E0 FF ....
while the data in FPGA was FF88 FF90 FF98 FFA0 FFA8 FFB0 FFB8 FFC0 FFC8 FFD0 FFD8 FFE0....
The data received were all repeated once .Why?
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Hi,
Did you actually probe and check the interface lines? Is the data actually going twice? What is the logic that you are using for transferring the data from FPGA? Iw woudl like to take a look at the GPIF state machine, and the code snippet that create many-to-one channel. Please attach the same.
Regards,
Gayathri
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SORRY,I got the wrong GPIF frequencey on PCLK
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Hello!
I need to receive data on bus 16 bit, and pack them into words by 1024. How can this be done at the state machine GPIF II?
I can not solve the problem of day 3.
Thanks in advance!