- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Please go through bulkloop example given in EZ-USB Development Kit User Guide vailable at C:\Cypress\USB\CY3684_EZ-USB_FX2LP_DVK\1.0\Documentation after installing FX2LP DVK.
Regards
Prajith
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
i read and tested it and it didn`t have any problem, but when i changed it to save recieving data to memory(or registers) and send the saved data from memory(or registers) , the data shifted several bytes like the picture( that i uploaded it here)! 😞
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi
i`m trying to transfer data from fx2lp(usb) to FPGA and vice versa.
i searched for an example and found "EZ-USB Technical ReferenceManual " and a simple VHDL code
for bulk loop data transfer. in this code FPGA gets data from FX2LP and saves it in a variable. then adds variable with 1
and gives it to FX2LP.
until here i haven`t any problem, but when i save recieving data in a memory in the FPGA and then i send it to FX2LP,
the recieved data(pc side) shifted like the picture that i uploaded in my first post 😞
...
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi,
this document is a part of "EZ-USB Technical ReferenceManual " and the code is same as one that
i said in my previous post!
i don`t have any problem with this code! it works correctly , but when i changed it for my purpose, it doesn`t
work correctly.
this is the cypress main VHDL code :
----------------------------------------------------------------------------------
-- Company: Cypress Semiconductors
-- Engineer: Hridya Valsaraju
--
-- Create Date: 03:28:52 12/18/2009
-- Design Name: FX2LP-FPGA interface
-- Module Name: test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fpga_master is
Port (
fdata : inout STD_LOGIC_VECTOR(7 downto 0); -- FIFO data lines.
faddr : out STD_LOGIC_VECTOR(1 downto 0); -- FIFO select lines
slrd : out STD_LOGIC; -- Read control line
slwr : out STD_LOGIC; -- Write control line
gstate : out STD_LOGIC_VECTOR(3 downto 0); -- debug lines
RESET : out STD_LOGIC;
led : out std_logic_vector(11 downto 0);
flagd : in STD_LOGIC; --EP6 full flag
flaga : in STD_LOGIC; --EP2 empty flag
clk : in STD_LOGIC; --Interface Clock
sloe : out STD_LOGIC --Slave Output Enable control
);
end fpga_master;
architecture rtl of fpga_master is
signal faddr_i : STD_LOGIC_VECTOR(1 downto 0);
signal slrd_i : STD_LOGIC;
signal slwr_i : STD_LOGIC;
signal cnt : std_logic_vector(7 downto 0):=(others=>'0');
signal gstate_i : STD_LOGIC_VECTOR(3 downto 0);
signal MasterState : STD_LOGIC_VECTOR(3 downto 0); -- Counter to sequence the fifo signals.
signal sloe_i : STD_LOGIC;
--shared variable cnt : integer range 0 to 9 := 0 ;
CONSTANT A: STD_LOGIC_VECTOR (3 DownTo 0) := "0000";
CONSTANT B: STD_LOGIC_VECTOR (3 DownTo 0) := "0001";
CONSTANT C: STD_LOGIC_VECTOR (3 DownTo 0) := "0010";
CONSTANT 😧 STD_LOGIC_VECTOR (3 DownTo 0) := "0011";
CONSTANT E: STD_LOGIC_VECTOR (3 DownTo 0) := "0100";
CONSTANT F: STD_LOGIC_VECTOR (3 DownTo 0) := "0101";
CONSTANT G: STD_LOGIC_VECTOR (3 DownTo 0) := "0110";
CONSTANT H: STD_LOGIC_VECTOR (3 DownTo 0) := "0111";
begin
RESET <= '1';
slrd <= slrd_i;
slwr <= slwr_i;
faddr <= faddr_i;
gstate <= not(gstate_i);
sloe <= sloe_i;
led(3 downto 0) <= not(slrd_i & slwr_i & faddr_i);
led(11 downto 4) <= not(cnt);
process(clk)
variable fifodatabyte : STD_LOGIC_VECTOR(7 downto 0);
begin
if(rising_edge(clk)) then
case MasterState(3 downto 0) is
when A =>
sloe_i <= '1'; -- IDLE STATE
faddr_i <= "00";
slrd_i <= '1';
slwr_i <= '1';
MasterState <= B;
gstate_i <= "0001";
cnt<=(others=>'0');
when B =>
faddr_i <= "00";
if (( flaga = '1' ) AND (flagd = '1') ) then -- IF EP2 is not empty and EP6 is not full and there is data waiting to be written into EP6
slrd_i <= '0'; --assert SLRD to read a byte from EP2
sloe_i <= '0';
fdata <= "ZZZZZZZZ";
cnt<=cnt+1;
MasterState <= C;
else
slrd_i <= '1'; --else go back to IDLE
sloe_i <= '1';
MasterState <= A;
end if;
slwr_i <= '1';
gstate_i <= "0010";
when C =>
fifodatabyte := fdata + '1' ; -- data processing state
faddr_i <= "00";
slrd_i <= '1';
slwr_i <= '1';
sloe_i <= '1';
gstate_i <= "0100";
MasterState <= D;
when D =>
fdata <= fifodatabyte; --place the data on the data bus
faddr_i <= "10";
slrd_i <= '1';
slwr_i <= '1';
sloe_i <= '1';
gstate_i <= "0101";
MasterState <= E;
when E =>
faddr_i <= "10";
slrd_i <= '1';
sloe_i <= '1';
if (flagd = '1') then
slwr_i <= '0'; --assert slave write control signal
else
slwr_i <= '1';
end if;
gstate_i <= "0110";
MasterState <= A;
when others =>
faddr_i <= "00";
slrd_i <= '1'; --if an undefined state move to IDLE
sloe_i <= '1';
slwr_i <= '1';
gstate_i <= "1000";
MasterState <= A;
end case;
end if;
end process;
end rtl;
and this is my code:
----------------------------------------------------------------------------------
-- Company: Cypress Semiconductors
-- Engineer: Hridya Valsaraju
--
-- Create Date: 03:28:52 12/18/2009
-- Design Name: FX2LP-FPGA interface
-- Module Name: test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fpga_master is
Port (
fdata : inout STD_LOGIC_VECTOR(7 downto 0); -- FIFO data lines.
faddr : out STD_LOGIC_VECTOR(1 downto 0); -- FIFO select lines
slrd : out STD_LOGIC; -- Read control line
slwr : out STD_LOGIC; -- Write control line
gstate : out STD_LOGIC_VECTOR(3 downto 0); -- debug lines
RESET : out STD_LOGIC;
led : out std_logic_vector(11 downto 0);
flagd : in STD_LOGIC; --EP6 full flag
flaga : in STD_LOGIC; --EP2 empty flag
clk : in STD_LOGIC; --Interface Clock
sloe : out STD_LOGIC --Slave Output Enable control
);
end fpga_master;
architecture rtl of fpga_master is
COMPONENT memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0):=(others=>'0');
signal addra : STD_LOGIC_VECTOR(9 DOWNTO 0):=(others=>'0');
signal dina : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others=>'0');
signal addrb : STD_LOGIC_VECTOR(9 DOWNTO 0):=(others=>'0');
signal doutb : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others=>'0');
signal addra_sig : STD_LOGIC_VECTOR(10 DOWNTO 0):=(others=>'0');
signal addrb_sig : STD_LOGIC_VECTOR(10 DOWNTO 0):=(others=>'0');
signal wr_full : STD_LOGIC:='0';
signal faddr_i : STD_LOGIC_VECTOR(1 downto 0);
signal slrd_i : STD_LOGIC;
signal slwr_i : STD_LOGIC;
signal cnt : std_logic_vector(7 downto 0):=(others=>'0');
signal gstate_i : STD_LOGIC_VECTOR(3 downto 0);
signal MasterState : STD_LOGIC_VECTOR(3 downto 0); -- Counter to sequence the fifo signals.
signal sloe_i : STD_LOGIC;
--shared variable cnt : integer range 0 to 9 := 0 ;
CONSTANT A: STD_LOGIC_VECTOR (3 DownTo 0) := "0000";
CONSTANT B: STD_LOGIC_VECTOR (3 DownTo 0) := "0001";
CONSTANT C: STD_LOGIC_VECTOR (3 DownTo 0) := "0010";
CONSTANT 😧 STD_LOGIC_VECTOR (3 DownTo 0) := "0011";
CONSTANT E: STD_LOGIC_VECTOR (3 DownTo 0) := "0100";
CONSTANT F: STD_LOGIC_VECTOR (3 DownTo 0) := "0101";
CONSTANT G: STD_LOGIC_VECTOR (3 DownTo 0) := "0110";
CONSTANT H: STD_LOGIC_VECTOR (3 DownTo 0) := "0111";
begin
RESET <= '1';
slrd <= slrd_i;
slwr <= slwr_i;
faddr <= faddr_i;
gstate <= not(gstate_i);
sloe <= sloe_i;
led(11 downto 10) <= "00";
process(clk)
variable fifodatabyte : STD_LOGIC_VECTOR(7 downto 0);
begin
if(rising_edge(clk)) then
case MasterState(3 downto 0) is
when A =>
sloe_i <= '1'; -- IDLE STATE
faddr_i <= "00";
slrd_i <= '1';
slwr_i <= '1';
MasterState <= B;
gstate_i <= "0001";
cnt<=(others=>'0');
when B =>
wea<="0";
faddr_i <= "00";
if (( flaga = '1' ) AND (flagd = '1') ) then -- IF EP2 is not empty and EP6 is not full and there is data waiting to be written into EP6
--assert SLRD to read a byte from EP2
fdata <= "ZZZZZZZZ";
if(wr_full='1') then
MasterState <= F;
else
MasterState <= C;
sloe_i <= '0';
end if;
else
slrd_i <= '1'; --else go back to IDLE
sloe_i <= '1';
MasterState <= A;
end if;
slwr_i <= '1';
gstate_i <= "0010";
when C =>
cnt<=cnt+1;
dina <= fdata + 2 ;
addra <= addra_sig(9 downto 0);
if(addra_sig<1023) then
addra_sig <= addra_sig+1;
wea<="1";
else
led(9 downto 0) <= (addra_sig(9 downto 0));
wr_full<='1';
addra_sig <=(others=>'0');
wea<="1";
end if;
sloe_i <= '1';
slrd_i <= '0';
MasterState <= F;
when F => -- data processing state
faddr_i <= "00";
slrd_i <= '1';
slwr_i <= '1';
sloe_i <= '1';
wea<="0";
gstate_i <= "0100";
if(wr_full='1') then
MasterState <= D;
else
MasterState <= B;
end if;
when D =>
addrb <= addrb_sig(9 downto 0);
if(addrb_sig<1023) then
addrb_sig <= addrb_sig+1;
else
wr_full<='0';
addrb_sig <=(others=>'0');
end if;
MasterState <= G;
when G =>
fdata <= doutb; --place the data on the data bus
faddr_i <= "10";
slrd_i <= '1';
slwr_i <= '1';
sloe_i <= '1';
gstate_i <= "0101";
MasterState <= E;
when E =>
faddr_i <= "10";
slrd_i <= '1';
sloe_i <= '1';
if (flagd = '1') then
slwr_i <= '0'; --assert slave write control signal
else
slwr_i <= '1';
end if;
gstate_i <= "0110";
MasterState <= A;
when others =>
faddr_i <= "00";
slrd_i <= '1'; --if an undefined state move to IDLE
sloe_i <= '1';
slwr_i <= '1';
gstate_i <= "1000";
MasterState <= A;
end case;
end if;
end process;
mem : memory
PORT MAP (
clka => clk,
wea => wea,
addra => addra,
dina => dina,
clkb => clk,
addrb => addrb,
doutb => doutb
);
end rtl;