Anonymous
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Jun 23, 2013
10:17 AM
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Jun 23, 2013
10:17 AM
Hi,
I'm using GPIF at master mode, with CS and WR/RD signal output. The slave will drive data when CS and RD are low at rising edge of PCLK. When the PCLK frequency is below 60MHz, there is no problem. However if the frequency goes higher than 60MHz, the data could not be sampled correctly, due to the delay of slave driving data. Is it possible to output CS and RD at rising edge and sample data at falling edge?
Thanks!
Rover
2 Replies
Anonymous
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Jun 24, 2013
01:10 AM
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Jun 24, 2013
01:10 AM
Hi Rover,
Did you try setting the "Active clock edge" field in GPIFII designer to Negative? This is effectively like inverting the PCLK before sending it out to your slave. So your slave will operate on rising edge and FX3 will operate on falling edge. I believe this might solve your issue.
Regards
Shashank
Anonymous
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Jun 26, 2013
12:41 PM
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Jun 26, 2013
12:41 PM
Hi Shashank, The point is not clock edge polarity, but the sampling time. The GPIF will sample data immediately when CS and RD are active. But there is delay when slave detected active read operation and output data to bus. For example, CS and RD become 0 at t0, then GPIF will sample data at t0, however, the slave detected read at t0 and output data at t1. Regards, Rover