SlaveFIFO 32 bit error

[Anonymous]

 Hello,

   

I am using FX3 as a Device controller used for USB3.0 communication with PC. I'm interfacing an FPGA xilinx Spartan6 to the FX3 with the slave fifo 32 bit by GPIG II  following the the guide of the website. For testing communication I'm using the loopback example of AN65974 downloaded folder and I custmoized the GPIF for my board with the GPIF tool . With the USB Control Center  I stream data to the FPGA and it write back to the fifo correctly (I can watch them with chiscpope analyzer). Something fails in the communication from fx3 to pc. In the the attached file you can see  the error in the 4th byte of 3rd line, 5th line, 7th line and so on.

   

Each line of the GPIO are right routered to the FPGA and equalized, I don't think there are problem with signal integrity. The hardware it seems ok.

   

Could you help me please?

   

thanks a lot

[Anonymous]

 I have exactly the same problem. I have rewritten the FPGA code without success.

   

Is there any silicon bug or path to the software?

   

We are changint the USB controller (for our project) because we did't fuond any solution.

[Anonymous]

Hi cusialbi,

   

Let's analyze the data.

   

32-bit word on GPIF bus before error is 1C 1D 1E 1F  (2nd row, bytes 13...16)
last byte in binary: 0001 1111

Next 32-bit word on bus is assumed to be 20 21 22 23  (3rd row, bytes 1...4)
last byte in binary: 0010 0011

But FX3 seems to capture this last byte as 0011 0011 (33 in hex) - 4th bit is high like in previous word on bus. For next 32-bit word after that, this 4th bit has correctly settled to 0.  All the errors are exactly the same. The same bit of 32-bit word seems to go from 1 to 0 too slowly. This is very characteristic of  timing errors.

   

You don't think there are problem with signal integrity. But, have you verified that FPGA output indeed fulfills FX3 data setup requirement?

   

Best regards,

   

kalev

[Anonymous]

Hi,

   

I totally agree with the reasoning that has been given by kalev.

   

This is definitely a timing related issue.

   

Thanks,

   

sai krishna.

[Anonymous]

 Thank you for the reply,

   

the problem is exactly that, I'll try to solve it.

   

Best regards

[Anonymous]

 Ok I solved it. I simply set the time constraints of the data bus tightly and it works perfectly now.

   

Thank you very match Kalev and RSKV

[Anonymous]

I also use FX3 as a Device controller used for USB3.0 communication with PC, and connect the Fpga to the FX3 with the slave fifo 32 bit by GPIF II. 

   

I used SDK 1.2.3, 

   

firmware: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.2\firmware\slavefifo_examples\slfifosync , 

   

application: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.2\application\cpp\bulkloop , 

   

, I've modified 

   

#define CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT  (1) 

   

in the cyfxslfifosync.h.

       

I send the data 0x2, 0x3, 0x4, 0x5,......, incrementing from PC, 

   

we expect the data of GPIF DATA BUS is 05040302, 09080706, 0d0c0b0a, ....., 

   

but the actual data is 00000302, 00000504, 00000706, 00000908, ...., 

   

In the the attached file you can see the captured data from chipsope.

   

I don't know how to fix that. 

   

Thanks a lot.