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The PSoC 3 kit-030 datasheet recommends not to use a VDDD higher than VDDA..... What is the reason for that?
Regards.
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The digital control V of an analog transmission gate is limited by gate ox
breakdown and parasitic diode turn on in non isolated well chip designs.
Additionally Vgs wants to be as high as possible, within those constraints,
to obtain max turn on, thereby resulting in higher switching speed and drive,
hence lower power. And to achieve min Rdson where ohmic switch performance
is paramount.
The goal of all this is to achieve higher Vg than analog in the transmission gate
where possible. Subject to noise feedthru, etc..
Tradeoffs, always tradeoffs.
Regards, Dana.
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To cite from the PSoC3 Architecture TRM:
Vdda must be greater than or equal to all other power supply pins (Vddd, Vddios) in PSoC 3. This power supply condition is required for the proper ON/OFF condition of the analog switches inside the device, and also for the implementation of the internal level switching logic when signals transition between multiple supply voltage domains.
(page 136)
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At its most basic level analog switching and routing govern the basic
CMOS analog switch characteristics, as well as device geometry.
Reference -
www.analog.com/library/analogdialogue/archives/31-3/ask.html
There are techniques, like gate drive boost converters, to get high
switch gate drive out of low core voltages, but as always tradeoffs
are incurred. Boost generaly implies more digital noise coupled
thru Cgd, Cgs in the switch.
Regards, Dana.
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The digital control V of an analog transmission gate is limited by gate ox
breakdown and parasitic diode turn on in non isolated well chip designs.
Additionally Vgs wants to be as high as possible, within those constraints,
to obtain max turn on, thereby resulting in higher switching speed and drive,
hence lower power. And to achieve min Rdson where ohmic switch performance
is paramount.
The goal of all this is to achieve higher Vg than analog in the transmission gate
where possible. Subject to noise feedthru, etc..
Tradeoffs, always tradeoffs.
Regards, Dana.
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olryt....so the reason goes deep into the CMOS switching features.......Anyways, I get it...Thanks for explaning this.
However, assuming that a certain application requires the digital bank to work at a voltage higher than that of the analog bank...can anything be done in PSoC for this particular case?
Regards.
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Or you run everything on the higher voltage, use voltage dividers on the analog inputs (if they are needed for some reason) and limit the outputs to the voltage you want.
Actually I don't see any need for that scenario - what would be a reason tu run the analog section at a lower voltage than the digital one?
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Even I dont need a higher VDDD...but I was just assuming it [you know, hptothetically ]: just in case we need to...!!!!!
Regards.