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Hi,
need to kno what is the actual minimum value of voltage Vssa in CY3866AXI-040. the datasheet specifies it as gnd +/- 0.5V but in the attached project of PGA the swing am seeing in the output is much below gnd at high gain value.Kindly see the attached file.
I've also seen the swing with a naked opamp in the same project, amplification is seen peak to peak an dnot above gnd.
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PSoC 3
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1. What is the voltage you are giving in P0[3] pin?
2. Where is it specified that Vssa can be GND+/- 0.5V?
3. It is definitely not possible to get -ve voltage out of PSoC as the lowest potential for the device is 0V only. How much low are you seeing at the output?
4. Why don't you specify the voltage values you are seeing on different pins of your project?
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If you have an ohmic path from Vssa to the point at which you observe the OpAmp
output refered to that ground point then you will see swings below ground. That
usually would be caused by poor layout, high current in Vssa ground path, poor
contact. The Vssa spec, as with virtually any CMOS pin, is controlled by worst
case threshold voltage of parasitic diodes attached to pins on all virtuall all CMOS
devices.
The reference spec is as follows -
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GND+/- 0.5 was a mistake, Pls rectify..its Vssd instead!
input is fixed frequency 5K triangular pulse which 280mV Vp-p( 140mv above and 140mV below gnd nearly). Gain settings can be seen in the main .c code which is attached with the project. an 8 bit variable can set PGA gain values among unity, 2, 8, 16 and 24 through USBUART. I've observed that-
> at unity gain 100mV above gnd with retained peak and 40mv below gnd with peak clipped off
>at 2 times gain 200mV above gnd with retained peak and 80mV below gnd with peak clipped.
> at 24 times gain 2.5V above gnd and 1V below gnd peak clipped
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and for the opamp( opamp_3) in the schematic was used just to test the maximum swing in the output from Vdda to Vssa. Same pulses as mentioned in OP were fed to PIN1_6 of the opamp which is non inverting terminal while the inverting is external gnd.
the output is Vp-p 4.8V square wave with 2.4V above 2.4V well below gnd.
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Don't think you should have signal below 0V. We normally have a "virtual" ground which is 1/2 Vcc for analog signals.
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The OpAmp intrinsically cannot swing below its output Vssa rail, otherwise
it is a free energy generaor we should all be using. However input can common
mode below Vssa, but not much.
So if you have a signal, fed o Vssa, that swings blow ground, and you do not want it
clipped/distorted then you have to meet both CMR on input and output. You do this
by offsetting input so that it meets both input CMR and G x Vin output CMR.
Two resistors can accomplish this, see attached calculator spreadsheet and article.
http://www.psocdeveloper.com/forums/viewtopic.php?t=3839
Regards, Dana.
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