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Hi
I want to know the connection of the resistance between the memory and FPGA. how the resistance are placed and connected to each other.
Thanking you
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Hi Subashbabu,
The attached article has the schematic of QDR SRAMs interfaced with FPGA. It can support 1.5V and 1.8V I/O voltages (VDDQ) and it supports HSTL-I I/O standard. For more details, please refer the application note, AN42468 .
Thanks
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Hi
Can i have the diagram representation of the connection the resistance the voltage levels and io-standrads
Thanking you
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Hi Subashbabu,
The attached article has the schematic of QDR SRAMs interfaced with FPGA. It can support 1.5V and 1.8V I/O voltages (VDDQ) and it supports HSTL-I I/O standard. For more details, please refer the application note, AN42468 .
Thanks