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Hello,
I may have a 'silly' doubt about using the software (APIs) to modify clocks and frequencies, which is: how to set the the PLL as the source of the Masterclock, and changing the divider thorought the code.
At the moment I have the following code, but it does not work as expected:
CyPLL_OUT_SetSource(CY_PLL_SOURCE_IMO);
CyPLL_OUT_SetPQ(15,1, 4);
CyMasterClk_SetSource(CY_MASTER_SOURCE_PLL);
CyFlash_SetWaitCycles(5);
CyDelayFreq(5000000);
CyMasterClk_SetDivider(14);
Any suggestions?
Best
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PSoC 3
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Consider posting a CASE on this -
“Support”
“Technical Support”
“Create a MyCase”
I looked at TRM, ap notes, seems to be a deficit of info.
Regards, Dana.
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I do see a lot of clock APIs in cyPm.c, you might take a look at notes
attached to the APIs to see if you can deduce a method.
Regards, Dana.
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At the moment the following code is working:
//PLL config
CyPLL_OUT_SetPQ(15,1, 4);
CyPLL_OUT_SetSource(CY_PLL_SOURCE_IMO);
CyPLL_OUT_Start(1);
//BUS clock
CyMasterClk_SetSource(CY_MASTER_SOURCE_PLL);
CyFlash_SetWaitCycles(5);
CyDelayFreq(5000000);
Best,
Chang
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*After the "CyDelayFreq" function, I forgot to post this line:
CyMasterClk_SetDivider(8);