16 Bit Datapath Chaining for simple Subtration.

[Anonymous]

        I have been trying to design a 16 bit Datapath for simple subtraction routine. It was pretty simple with an 8 bit datapath but somehow I can not figure out how to build a 16 bit one. I guess the problem is with status register signals from the Verilog module that indicate that calculation has been completed. Can someone here look at it and identify the exact problem? I am attaching the bundle. I will be grateful for a response.   

[HeLi_263931]

There are two posts which might help you:
Data path super primitives which has pre-made components for 8, 16, 24 and 32 bit data path components
Datapath Chaining Cheat Sheet which helps when chaining components

[HeLi_263931]

        Sorry, I messed up the second link (after two weeks vacation the first thing I get to see here is this stupid text box 😞 So here you go: http://www.cypress.com/?app=forum&id=2492&rID=76862