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Hi there,
I am new to PSoC4 platform...Can anyone tell me if there are any limitations/constraints in PSoC 4 (similar to a lower max CPU clock in some PSoC 1 devices) while working at 1.8V??
Thanks,
Rahul
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Look at the PSoC4 (4200 familiy) data sheet: http://www.cypress.com/?docID=44456
On page 15, the maximum CPU frequency is specified as 48MHz over the full Vdd range (1.71-5.5V).
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The limitations I can see are:
- current one can draw from an OpAmp (Table 😎
- SWD frequency (Table 37)
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You have to read both datasheet and specific component datasheet to get insight
into V effects, Some like -
1) Noise Margin
2) GPIO Toggle rates
3) Power
4) CMRR
There are some graphs in individual component datasheets for review as well.
No doubt the rout timing is also affected as CMOS device characterisitics also
change with supply.
Regards, Dana.