Limtations/constraints in PSoC4 @ 1.8V operation??

Look at the PSoC4 (4200 familiy) data sheet: http://www.cypress.com/?docID=44456

On page 15, the maximum CPU frequency is specified as 48MHz over the full Vdd range (1.71-5.5V).

The limitations I can see are:

    
• current one can draw from an OpAmp (Table 8)
    
• SWD frequency (Table 37)
   

You have to read both datasheet and specific component datasheet to get insight

into V effects, Some  like -

1) Noise Margin

2) GPIO Toggle rates

3) Power

4) CMRR

There are some graphs in individual component datasheets for review as well.

No doubt the rout timing is also affected as CMOS device characterisitics also

change with supply.

Regards, Dana.