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1. Re: Limtations/constraints in PSoC4 @ 1.8V operation??
helic_263931 Aug 22, 2013 1:43 PM (in response to rahulg_)Look at the PSoC4 (4200 familiy) data sheet: http://www.cypress.com/?docID=44456
On page 15, the maximum CPU frequency is specified as 48MHz over the full Vdd range (1.71-5.5V).
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2. Re: Limtations/constraints in PSoC4 @ 1.8V operation??
helic_263931 Aug 22, 2013 1:46 PM (in response to rahulg_)The limitations I can see are:
- current one can draw from an OpAmp (Table 8)
- SWD frequency (Table 37)
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3. Re: Limtations/constraints in PSoC4 @ 1.8V operation??
DaKn_263916 Aug 22, 2013 3:20 PM (in response to rahulg_)You have to read both datasheet and specific component datasheet to get insight
into V effects, Some like -
1) Noise Margin
2) GPIO Toggle rates
3) Power
4) CMRR
There are some graphs in individual component datasheets for review as well.
No doubt the rout timing is also affected as CMOS device characterisitics also
change with supply.
Regards, Dana.