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A PDM Algorithm Based On Addition
This algorithm is described in my Chinese blog “A PWM Algorithm For Software And Hardware Realized With Only One Add Instruction”. And an example implemented by hardware (UDB datapath) and software respectively on PSoC 4 pioneer kit is also included - ZhuPDM8(PSoC Creator 2.2 SP1).rar .
The blog is written in Chinese , but the programming language is common.
http://files.chinaaet.com/files/blog/2013/07/21/ZhuPDM8(PSoC%20Creator%202.2%20SP1).rar
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What's wrong?
MATLAB shows the duty cycle is 50% for N=2 and H=1:
>>
npulse = 8;
N = 2;
H = 1;
CNT = 0;
disp( ' k Pout for init. CNT=0' )
for k = 1:npulse
CNT = CNT + H;
if CNT >= N
CNT=mod(CNT,N) ;
Pout = 1 ;
else
Pout = 0 ;
end
disp( [k Pout] )
end
k Pout for init. CNT=0
1 0
2 1
3 0
4 1
5 0
6 1
7 0
8 1
>> ...
k Pout for init. CNT=1
1 1
2 0
3 1
4 0
5 1
6 0
7 1
8 0
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The difference between the two condition is one with the % instruction, and the other does not.
My answer is runing it from a 'CPU'. The CPU needs to process the % instruction.
You can compile the code and check the difference of instructions.
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Hi H L,
I don't think there is any difference between the mod() and the %-operator.
The debug result (see attached screen copy) of following programm runing in a real CPU with the %-operator
shows the same duty cycle of 50%.
void main()
{
uint16 N = 2;
uint16 H = 1;
uint16 CNT = 1;
uint8 Pout[8];
uint16 k=0;
do {
CNT += H;
if (CNT >= N)
{ CNT %= N ; Pout
else Pout
k++;
}while(k<8);
for(;;) { }
}
May the defferent compiler cause the defferent result of %-operator ?
http://files.chinaaet.com/images/blog/2013/07/24/442064405399.jpg
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Assume there is a function delayInSeconds().
And added the call to the function in RED as in the following.
***********
do {
CNT += H;
if (CNT >= N)
{ CNT %= N ; delayInSeconds(99); Pout
else ( delayInSeconds(1) ; Pout
k++;
}while(k<8);
***********
you have a delay of 100 seconds in one condition and 1 second in other condition. The duty cycle is around 1%, but the array Pout[] didn't show that because it doesn't capature the time information.
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Sorry, a typo.
you have a delay of 99 seconds in one condition and 1 second in other condition. The duty cycle is around 1%, but the array Pout[] didn't show that because it doesn't capature the time information.
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Sorry for misunderstanding your meaning.
Is OK for following sentanses?
CNT += H;
if (CNT >= N)
{ Pout = 1 ; CNT %= N ;}
else Pout = 0 ;
or
CNT += H;
if (CNT >= N) Pout = 1 ;
else Pout = 0 ;
CNT %= N ;
But maybe some one says : the if-branch and the else-branch use different numbers of CPU instructions.
And even in hardware imlemention with datapath there still has the difference of a few nano-seconds
caused by the difference between the pulse rise time and the pulse fall time. The duty cycle is not 50% in absolutely accurate meaning.
In my blog above, i just give a principle of the algorithm in style of C. In the real projects, I usualy use assembly language for software realization, and always pay attantion to minimazing the number of instructions and the balance of instruction cycles between branches.
As i declared in my chinese blog, for the convinience of reading i do not use the assembly language to describe the algorithm.
Thank you for your precision of CPU instruction number level.
Any more difference between us ?
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The first one
********
CNT += H;
if (CNT >= N)
{ Pout = 1 ; CNT %= N ;}
else Pout = 0 ;
*************
Still has the same issue.
The second one
*********
CNT += H;
if (CNT >= N) Pout = 1 ;
else Pout = 0 ;
CNT %= N ;
****
doesn't has that issue.
My intention is not for the timing of different type of instruction as It would be different with CPU with branck prediction or newer and faster CPU with tricks to work faster. And I am not trying to argue about the ns different in rising or falling edge of the pulse.
My intention is that your orignal method of prove missing important information about the out come. For a fast CPU the different is very small. The bigger the number is N, the smaller is the error as well.
But as I mention before, it is a clever way to doing it.
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And as you mentioned. Using assembly language would give more accuray timming of the pulse.
A word of caution: The code is good as a concept. But in real life that with ISR or the PWM routine is part of a main loop, the timming would be complicate/inpossible to calculate.
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A PWM should at best be realized in hardware because that implementation is most safe and precise and can be independent of CPU or CPU load.
Nevertheless, when short of hardware or UDBs which can easy be the case in a PSoC4 a software-solution could help.
Depending on the desired frequency and granulation there are different solutions possible which will result in a different CPU load.
Since most systems run interrupt driven the precision can be affected by those, but if you take into account to run the software-PWM interrupt driven as well which limits the frequency by the time needed to satisfy the interrupt.
Minimizing the CPU-overhad would include to reduce the code needed, that would include thinking over how to eliminate a division-operation (the modulo %), so there are still points of optimization.
Having a good software solution for a PWM will help many of us engineers to relax when running short of resources.
Happy coding
Bob
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One more thing about this approach is that for ratio of x/y where x and y are relatively prime, x is not 1 and y is larger than x, the output with have jitter because the toggling point changes between cycles.
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All discussions above are helpful for me.
I found that my poor English is not enough to express my opinion correctly.
To avoid misunderstanding I will finish this topic on Cypress Forum.
Before finishing I’ll give a summary.
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Summary
1. History
My software-PDM was first used for DC-motor speed control in MCS-51 system since 1990 year and even earlier.
Some codes for 3 PDM-outputs were simply as following:
Timer_ISR:
...
;1 Timer for 3 PWM.
;Operation interval is determined by timer with higher priority.
;Default N=256, no mod-operation is needed.
;Each PDM-operation takes only a few CPU instruction cycles.
MOV A,CNT1
ADD A,H1
MOV CNT1,A
MOV Px.1,C
;
MOV A,CNT2
ADD A,H2
MOV CNT2,A
MOV Px.2,C
;
MOV A,CNT3
ADD A,H3
MOV CNT3,A
MOV Px.3,C
...
RETI
Why not hardware PWM?
No any hardware PWM could be used in that years, and the MCS-51 MCU had even no Timer2 at that time.
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2. Edge-to-Edge interval
Software-PDM generator is desired to run in a Timer_ISR. The edges of 0-t0-1 or 1-to-0 are ensured by Timer (if it is accurate enough), not by instruction numbers as in example running in the main loop.
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4. More about this algorithm
(1) Only a part of this algorithm is shown in this topic above :
N, H (0...N-1) are positive integers.
For some numbers as N=2^m, we use AND-operator instead of mod-operator for faster processing.
And even no any mod-operator is needed for N=256(8-bit ALU),N=65536(16-bit ALU),and so on.
(2) a little more - for software implementation only.
For n=1 and any positive real number h in [0,1), for example , h=0.123456789...or h= a fraction, and even h=1/pi or h=sqroot(1/2).
For positive real number Remainder with arbitrary initial value in [0,1), the software PDM-generator is as following:
Timer_ISR:
...
Remainder += h;
if (Remainder >= 1)
{ Pout = 1 ; Remainder -= 1 ;}
else Pout = 0 ;
...
END of Timer_ISR
Cutting a fragment with any length(N) at any point from the output pulse train, and counting the 1's number(H) in this fragment, you can find , that the ratio H/N is always the best fraction approximation of the real number h (comparing with same denominator N).
Sometime I called it as Software Delta-Sigma Output.
Jitter? No problem. A low-pass filter is waiting at output port.
A jitter is not always bad. Sometime, jitter will cut the noise peak and spread it.
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5. I'll continue my blog about this PDM-algorithm in Chinese.
All of you are welcome to visit and discuss there.
If I can't express my opinion in English, I can use Chinese there.
If I made any typo, I can edit it. I made many typos here, but I can't correct it, because Cypress Forum has no edit tool.
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1. a. Using timer interrupt to perform the operation is better. I think we were discussing with what you presented which is software instruction only.
b. I did program chips with 64 nibbles(not bytes) of RAM, no interrupt, 1 level of stack. and every function cannot be longer then 64 bytes. So I understand the need for these cleaver tricks.
2. See 1.a
3. Analog voltage generation is one of the application of PWM, the jitter is not a problem
for this usage, but may cause problem in other situations.
Again, using for LED driver is not a problem because the eye does the filtering.
4. a. See 1.a
b. Yes, it is like a delta sigma operation
5. A lot of people here is from non-English speaking country, so don't worry.
If we don't understand we would ask question to clarify.
Editing function has been requested for a long time already.
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The Priciple of The PWM Algorithm Based On Addition
- A PDM Algorithm Based On Addition (2)
http://blog.chinaaet.com/detail/33392.html in Chinese.
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Hardware PWM vs Hardware PDM Based On Addition
- A PDM Algorithm Based On Addition (3)
http://blog.chinaaet.com/detail/33470.html in Chinese.
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How to Realize the Hardware PDM with PSoC UDB
- A PDM Algorithm Based On Addition (4)
http://blog.chinaaet.com/detail/33508.html in Chinese.
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Nice Write up fyzhu, quite interesting use.
in chineese but fortunatelly there is chrome autotranslation 🙂
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The Origin Of The PDM Algorithm Based On Addition
- A PDM Algorithm Based On Addition (5)
http://blog.chinaaet.com/detail/33600.html in Chinese.