CY4531 CCG3 Daughter Card standalone USB usage

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mvic_2509051
Level 1
Level 1

Hi,

   

I have a CY4531 CCG3 Daughter Card which I am using standalone, without the CCG EVK Base Board.

To develop the software I use PSoC Creator 4.0 update 1. For I2C,SPI and UART I used the component catalog to add these components to the TopDesign.cysch. These components work fine I am able to control UART,I2C and SPI.

   

But now I am moving on to USB for this I have removed R48 and R49 from the CY4531 CCG3 Daughter Card and added 0E resistors on R51 and R52 and connected the USB Mini B (j7) to my PC.

   

In the component catalog there are only USB components which are incompatible (USBFS,USBMIDI,USBUART)
 so these I cannot use. What I do now in my own main is control the functions in usb.c from the SDK directly.

   
        
  1. call usb_init() with my own usb_config_t structure
  2.     
  3. call usb_enable()
  4.     
  5. call usb_task from the mainloop.
  6.    
   

When the program starts my pc detects a new device, so I see that the CY4531 USB block is started, but the enumeration fails.
Somehow the functions registered through usb_init's usb_config_t structure are never called

   

Is there something else that must be done to usb the USB block?

   

Regards

   

Marcel

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1 Solution
mvic_2509051
Level 1
Level 1

Hi,

   

Solved! Solution:
From PSoC Creator I created a new project based on EZ-PD CCGx SDK (CCG3) and selected 'Empty Schematic' as Project Template.
In the Design Wide Resources (.cydwr file) and on the clocks tab the IMO and HFCLK are set to 24MHz. These should be set to 48MHz for USB! Before (24MHz) only the event_cb function from the usb_config_t structure was called and running @ 48MHz get_dscr_cb is called. Filling this with the correct data I also see this on the PC. PC tool used http://www.uwe-sieber.de/usbtreeview_e.html

   

So Long, and Thanks for All the Fish
Marcel

   

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1 Reply
mvic_2509051
Level 1
Level 1

Hi,

   

Solved! Solution:
From PSoC Creator I created a new project based on EZ-PD CCGx SDK (CCG3) and selected 'Empty Schematic' as Project Template.
In the Design Wide Resources (.cydwr file) and on the clocks tab the IMO and HFCLK are set to 24MHz. These should be set to 48MHz for USB! Before (24MHz) only the event_cb function from the usb_config_t structure was called and running @ 48MHz get_dscr_cb is called. Filling this with the correct data I also see this on the PC. PC tool used http://www.uwe-sieber.de/usbtreeview_e.html

   

So Long, and Thanks for All the Fish
Marcel

   

0 Likes