ADC 18bit DMA to SRAM

[Anonymous]

Hi,

   

i have a problem with DMA. I split the DelSig ADC with a logic into two channels; A &B. That seems to work quite well. But the data I transfer with DMA doesn't look good. I am not sure if I need to use CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_INC_DST_ADR or not. If I use above configuration parameter for both channels, the values are static in the array (even if I feed the ADC with a sinus-signal). If I just write 0 configuration for both channels, the values seems to me nonsense and quite noisy even if the input voltage is stable.

   

After that DMA transfer I have some further transfers to feed values into DFB-Filter block.

   

An example for my code which is the same for channel B, is attached code example.

   

The goal of the logic with DMA transfer is to toggle between channel A and B. When 10 samples are full, I immediately transfer that SRAM -array to the next task with another DMA.

   

I hope someone can help.

   

BR

   

Rob

[Bob_Marlowe]

Welcome in the forum, Rob.

   

Have a look at these application notes.

       

Bob

[Anonymous]

thanks Bob. I read it before and now again. So now I am sure I need the configuration like this because of 16 bit spoke width:

   

CyDmaTdSetConfiguration(DMA_DelSig_A_TO_SRAM_TD[0], 3u, DMA_DelSig_A_TO_SRAM_TD[1], CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_INC_DST_ADR);

   

But I have still the problem from application note (001-84810_AN84810_-_PSoC_3_and_PSoC_5LP_Advanced_DMA_Topics.pdf) shown in "Figure 52. Misaligned Source Address – Destination Data Duplicate". Strange is that this problem is affecting two DMA transfers. I still cannot find the reason because I think my configuration is fine. See attached complete configuration code for both.

   

Does somebody see my fault?

   

thanks a lot.

   

Rob

[Bob_Marlowe]

Why don't you use just 2 DMAs, one for each channel and 2 TDs, one for each DMA. Generate the DMA request signal by gating the ADCs eoc to the right DMA. CY_DMA_TD_INC_SRC_ADR is darn wrong! The ADC result is always in the same register, so no increment to the next location required.

   

Can you please post your complete project so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.

       

Bob

[Anonymous]

Hi Bob,

   

please find my relevant code attached. I deleted INC_SRC but without the data look odd. I read in this report https://www.hackster.io/bmah/psoc-5lp-16-bit-and-24-bit-digital-filter-code-examples-ddcf9c and used it too. When I do it for one channel (e.g. A) and the other I set both config values 0 it seems to work. Quite confusing!

   

I am looking forward for your support.

   

thanks.

   

Rob

[Anonymous]

Hi Rob,

   

I checked the code and seems like the DMA configurations are correct. Please just try changing the bytes per burst and TD length to 4 instead of 3. As peripheral is only 16 bit wide and you want to transfer 18 bits data, you need to increment Source Address. But I have one question - can you explain what is meant by "config values 0"? 

   

Also, why would you like to implement using 10 TDs? 

   

Please check: section "20-Bit ADC Data Buffering Using DMA" in:

   

http://www.cypress.com/documentation/application-notes/an61102-psocr-3-and-psoc-5lp-adc-data-bufferi...

   

You just need 2 DMA channels with one TD each. You can make use of the intermediate SRAM to store the full 32 bit data and then move to the buffer (TD length of the buffer depends on how many samples you need to store)? Is it possible to change your firmware to this way?

[Anonymous]

Hi BMAH,

   

thanks.

   

Well, I mean regarding "config values" this:  if I use 0 instead of  CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_INC_DST_ADR

   

I decided to use 10 TDs because I use a filter afterwards. The problem is that I need the same time stamps of ADC A and B. So I need to multiplex it. I could do the same with the filter, because it has two channels but I need the second channel for other operations. That is why I use a buffer and channel the data with DMA through the certain stages. Which seems to work ok but ADC DMA which I posted here.

   

I tried to change to 4 bytes per burst and TD length to 4 but I get random numbers (it looks like that).

   

Do you have another idea what might cause the problem?

   

thanks.