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As title says the SW Tx UART output is garbled after changing the clock frequency in code.
I am running on the CY8CKIT-042-BLE-A
ECO = 24 MHz
UART baud rate set in component to 19200
<code>
/* Internal low power oscillator is stopped as it is not used in this project */
CySysClkIloStop(); // This is actually already done in the clock settings in PSoC Creator, but this is how it is achieved in code.
/* Set the divider for ECO, ECO will be used as source when IMO is switched off to save power */
CySysClkWriteEcoDiv(CY_SYS_CLK_ECO_DIV8); // --> Provides a 3 MHz clock. Lowest clock acceptable for SW Tx UART component.
/* change HF clock source from IMO to ECO, as IMO is not required and can be stopped to save power */
CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_ECO);
/* stop IMO for reducing power consumption */
CySysClkImoStop();
/* CySysFlashSetWaitCycles can optionally be called after lowering SYSCLK
* clock frequency in order to improve the CPU performance. */
CySysFlashSetWaitCycles(3); // Frequency in MHz
/* Update Delay frequency as clock frequency has changed */
CyDelayFreq(3000000UL);
</code>
I output some debug to the UART and it outputs fine before i change the clocks.
I thought that it should be enough to call CyDelayFreq when changing the freq.
Do I miss something ?
br,
Martin
Solved! Go to Solution.
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I found the solution.
I falsely believed the EcoDiv was the divider for the SYSCLK, but is it for the HFCLK.
And since the SYSCLK divider was set to 2 in the settings, the clock got divided further down to 1.5 MHz.
So i added the line:
/* Change Prescaler for SYSCLK - set to 1, since ECO is already divided by 8*/
CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV1);
After setting ECO as HFCLK source.
br,
Martin
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I found the solution.
I falsely believed the EcoDiv was the divider for the SYSCLK, but is it for the HFCLK.
And since the SYSCLK divider was set to 2 in the settings, the clock got divided further down to 1.5 MHz.
So i added the line:
/* Change Prescaler for SYSCLK - set to 1, since ECO is already divided by 8*/
CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV1);
After setting ECO as HFCLK source.
br,
Martin