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Device: S25FL256SAGMF1000
Hi!,
I'm using an STM32F765 in Quad QSPI mode with the command QIOR (EBh) to read the S25FL256S.
However, all bytes look like 0x88 !
Is there a status read command I can use in QSPI mode ?
The device is a new part and the problem is on more than one board.
I have attached a signal trace of CS, SCK, IO0, IO1, IO2, IO3 (Read capture.png)
What could be wrong please?
Solved! Go to Solution.
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Hello Krishna,
I have solved the problem. It was the dummy cycles for read command.
I set dummy cycles to 3 for 12.5Mhz clock.
I'm using 3 bytes addressing.
Many thanks for your help.
Julian
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Hello,
For the QIOR command (EBh) to work, QUAD bit (CR1[1])in configuration register must be set to 1. It will enable the quad capabilities of S25FL256S. Are you setting this bit before performing QIOR operation? Please let us know the below details also.
1. What is the frequency at which you are operating our device?
2. What is the value of LC (latency code) bits set in configuration register?
3. Are you observing this issue in all the devices?
4. What is the data you are expecting for the flash device?
Thanks and Regards,
Sudheesh
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Hi Sudheesh,
Thanks for your reply.
I've implemented setting of the CR1[1] bit to 1 and LC = 2.
Frequency of clock is 12.5Mhz
It is improved now. I read all FF's
I'm using QPP (32h) to program 16 bytes.
However, QPP write fails to work even after waiting for the WEN bit in SR1 to go to 1.
Regards,
Julian
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Hello Julian,
Since the frequency of operation is less than 50MHz the latency code LC bits has to be 3 (11) . Please refer tables on page 52 of datasheet.
Please change the LC and check if you are observing the same issue.
Thanks,
Krishna.
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Hi,
Changed LC bits to 3. Same result.
See below:
flashwrite
Write:0 1 2 3 4 5 6 7 8 9 A B C D E F
Status reg: 2 2
Write enabled (SR1 = WEN)
Write done
Flashread
Read: 88 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Thanks,
Julian
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Hello Julian,
Which operation you are performing to set WEL bit Status Register. Please note that Write register WRR(01h) will not work. You need to use WREN(06h) to enable the WEL bit. Hope you are using command WREN(06h).
Thanks,
Krishna.
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Hi Krishna,
Using WREN(06h)
Thanks,
Julian
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Hello Julian,
Can you please let us know the configuration register value. The status register value 2 2 ( 0010 0010 ) indicate that Erase error happened.
Just want to check incase if the sector is protected.
Thanks,
Krishna.
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Configuration register just QUAD_MODE (02h)
registers.status = 0; /* Default state */
registers.config = S25FL256_QUAD_MODE; /* Enable QUAD access mode */
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Hello Julian,
Are you able to read the Device ID of the device. ? Can you please check and let us know .
Thanks,
Krishna.
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Hello Krishna,
Now better results. I needed to use 1 line for address in read function.
Using QPP(0x32) for write and 0xEB for read.
However, data if offset by 1 byte
Dummy cycles on read = 5
Latency = 3
flashwrite
Write: addr: 0x00020000, sector 2
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Status reg: 0x02
Ok to write. SR1 = 02
Write done
flashread
Read: addr: 0x00020000, sector 2
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FF
Something not quite right yet.
Regards,
Julian
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Hello Julian,
How many times observe the shift behavior. Are you observing the same issue every time you try to write ?
I am nor sure why there is one byte shift. Can you erase the sector and try to write any other data and check if you are observing the same issue.
Make sure all the data is FF in the sector before you write.
One more clarification are you using 3 byte addressing or 4 byte addressing ?
Thanks,
Krishna.
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Hello Krishna,
I have solved the problem. It was the dummy cycles for read command.
I set dummy cycles to 3 for 12.5Mhz clock.
I'm using 3 bytes addressing.
Many thanks for your help.
Julian