Psoc4: Deep-sleep total power consumption with just LP comparators active

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Anonymous
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 I cannot find on psoc 4 datasheet info about power consumption when in deep-sleep mode and there's just a comparator active with voltage reference (either internal, IDAC... or external voltage) used to wakeup CPU. I can find just such info when in sleep mode (1200uA). On Psoc5LP there's such information (reported as 3uA): since I suppose the same manufacturing technology, is correct to assume a similar current? thanks

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ETRO_SSN583
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Since the core and memory substantially different I would not draw

   

that conclusion. Consider filing a tech case at -

   

 

   

"www.cypress.com"
"Support"
"Technical Support"
"Create a Case"
 

   

Regards, dana.

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HeLi_263931
Level 8
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When looking at the PSoC42xx family data sheet, I find nearly everything (assuming 3.3V supply and 25 degrees):

   
        
  • deep sleep current consumption is 1.3µA, page 15
  •     
  • comparator uses 6µA (in ultra-low-power mode), page 19
  •    
   

Unfortunately there is no spec for the voltage reference 😞 But it might be that it is always enabled, the I would expect it to be included in the deep sleep current consumption...

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ETRO_SSN583
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You might ask in the Tech Case for worst case numbers, typicals at room temp

   

generally not useful in worst case design.

   

 

   

Also looking at Register TRM for Bandgap there are a number of control registers.

   

You might get further info there.

   

 

   

Regards, Dana.

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HeLi_263931
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The data sheet also shows the worst case values (for the temp. range up to 85 degrees). Its then 50µA for deep sleep mode, and still 6µA for the comparator.

   

When looking for the bandgap data, the only reference I can find is that the is s separate voltage regulator for it. This implies to me that it is always enabled.

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ETRO_SSN583
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You could reference this in the tech case post to see if

   

PSOC 4 values now available for power estimator

   

spreadsheet -

   

 

   

http://www.cypros.org/?app=forum&id=4749&rID=83353

   

 

   

Regards, Dana.

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ETRO_SSN583
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The Bandgap is (from TRM) -

   

 

   

18.2.1 Precision Bandgap

   


The principle of the bandgap circuit relies on two groups of
diode-connected bipolar junction transistors running at dif-
ferent emitter current densities. By canceling the negative
temperature dependence of the PN junctions in one group of
transistors with the positive temperature dependence from a
Proportional-to-Absolute-Temperature (PTAT) circuit (which
includes the other group of transistors), a DC voltage that
changes very little with variations in temperature is gener-
ated. In this block, the current reference is also provided.

   

 

   

18.3 Configuration

   


During power-up, the precision reference block is initialized with default trim settings saved in nonvolatile latch (NVL) and
SFLASH. These settings are programmed during manufacturing and no field adjustment is needed.

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