Mater driving 64K SRAM

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Anonymous
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        I am trying to write a master configuration with 16 bit address and 16 bit data. The GPIF designer allocated the data bus to GPIO 15:0 and the address but to GPIO 49:46 and 27:16. isDQ32Bit is defined as true for IOMatrixConfiguration. For some reason, the upper for address bits located at GPIO49:46 do not seem to reflect the address. Addresses wrap around every 4K of data. Any ideas ? Any similar examples ?   
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Anonymous
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 Hi,

   

Please let me know how are you driving the address on to the address bus and also how are you saying that the address is getting wrapped for 4KB of data.

   

Is it possible for you share the project that you developed with us.

   

Thanks,

   

Sai Krishna.

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Anonymous
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        After some night work it seems that we know the answer. Looking at table 16 of the datasheet, DQ[31:28] are available at the pins only when 32bit GPIF and both UART and I2S are on. We do not use the I2S.   
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