- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I'm sending 16bit data using SPI without any delay between data. Thus, the SS line never switches high/low to denote the start and stop of data. This is causing errors on my slave device because it is expecting the SS line to pulse high between data.
I tried software solutions but the timing isn't accurate enough. Because my data is sent without delay the SS line pulse must fall between the falling edge of the 16th clock and the rising edge of the next clock cycle.
I'm looking for suggested solutions and for comments on my next attempted solution below.
I plan to to test a counter with the SPIM clock as input. The counter will count 16 clock cycles. Output of the counter will go into a rising edge detector. Both the counter and edge detector will use much faster clock than the SPIM. Output of the edge detector will be used for SS line. Seems like it may work from the datasheets. I'll post back with results.
- Labels:
-
PSoC 3
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Another approach would be to clone the component and make the changes in verilog. Will not be easy, but will at last perform correctly and independent of the selected baud-rate.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Can you add a small delay after sending each of the 16bit-words? (Or wait until sending one word has finished before you add the next wor d to the transmit FIFO)? That way the SPIM would handle the SS signal properly.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ok. I got some type of solution, but it's not ideal. I'll post detials of the solution once I confirm.
I now have multiple SS state changes between data transmits. I have a slave PSoC to simulate a slave ADC device, but I think the muliple SS toggles are causeing error, but I'm not sure of how the SPIS/SPIM devices work in detail. See attachment.
Would multiple SS state changes cause any problems? There are no clock cycles during the mulitple SS state changes between data transmits. Is the SS line limited to a single high state between data transmits and clock cycles?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I think most SPI devices would reset the internal state machine with a high on SS. But your device may use the line to increament the state machine counter to receive the next 8 bits. If that is the case, it would case problem. One thing you can try is to control the SS line yourself to get one clean transition between the 2 bytes.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Can you tell us what is the device that you use?