--> For example, If you start the first write at clock X then your write data will be presented on data bus at X+2 clock. In the linear write operation, the write data will be presented at every clock cycle so with respect to clock X, the write operation will be finished by clock X+5 (write data will be on X+2, X+3, X+4 & X+5) but if you break down this linear write operation in to the single write operation then with respect to clock X+1 write operation, your second write will happened on clock X+3, similarly with respect to clock X+2, the write data will be presented on clock X+4.
So, single write operation always takes 2 clock cycles but linear 4x write burst will take 5 clock cycles to write with respect to the first write command. Please refer Figure 4 of the datasheet (http://www.cypress.com/?docID=40032), you will get an clear idea from first three write operations.
--> Yes, you can connect /CE1 and /CE3 to ground and use CE2 for chip enable because chip is enabled when /CE1 is LOW, CE2 is HIGH and /CE3 is LOW.
And Chip is disabled when /CE1 is HIGH or CE2 is LOW or /CE3 is HIGH.
So you can use CE2 as your chip enable signal.